用Verilog实现卷积编码

用Verilog实现卷积编码 module convolution(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW,Error_SEL, MUX_CLK,error_ind,frame_ind,m_sel,m_test,MUX_DT); input FSX_PCM,BCLKT,DT_PCM,m_Sequence,MUX_CLK; input[1:0]m_sel,Error_SEL; input[7:0]SW; output error_ind,frame_ind,m_test,MUX_DT; reg all_zero,b,error_ind,frame_ind,m_test,MUX_DT; reg[6:0] temp; wire clk;