Introduction to Design for Testability

1 IntroducTIon to Design for Testability 1-1

2 Reasons for Using Design for Testability -1

The Need for Testability ..-2

Test-TIme Cost ..-2

TIme-to-Market ..-3

Fault Coverage and Cost of Ownership-5

3 Developing a Testability Strategy 3-1

SelecTIng a Technology.3-2

Committing to Testability Design Practices3-3

Establishing a Fault-Grade Requirement...3-4

Will IEEE Standard 1149.1 Be a System Requirement? 3-5

Selecting a Testability Approach Based on Gate Density.3-6

Choosing Structured Tools ....3-7

Establishing a Diagnostic Pattern Set to Expedite Debug3-9

Generating High-Fault-Grade Test Patterns ....3-10

Simulating Test Patterns and Timing 3-11

Converting Test Patterns to TDL ......3-12

Planning for Test Pattern/Logic Revision Compatibility 3-13

4 Test Pattern Requirements 4-1

Responsibilities4-2

TDL Type Descriptions .4-3

5 Ad Hoc Testability Practices 5-1

Logic Design With Testability in Mind .5-2

Improving Testability Via Unused Pins ......5-3

Using Bidirectional Pins5-4

Initializing the Circuit to a Known State .....5-5

Avoiding Asynchronous Circuitry.5-7

Avoiding Gated Clocks .5-8

Allowing Internal Clocks to Be Bypassed From Circuit’s Inputs....5-9

Allowing Counters and Dividers to Be Bypassed ..5-10

Splitting Long Counter Paths.....5-11

Multiplexing to Provide Direct Access to Logic 5-12

Breaking Feedback Paths in Nested Sequential Circuits5-14

Allowing Redundant Circuitry to Be Tested .....5-15

Watching for Signals That Reconverge ...5-16

Decoupling Linked Logic Blocks5-17

Johnson Counter Test Signal Generator .5-18

Shift Register Test Signal Generator 5-19

Shift Register Used to Obtain Observability ....5-20

6 Structured Testability Practices 6-1

Structured Approaches to Designing for Testability .6-2

Clocked Scan Flip-Flop Design ...6-3

Multiplexed Flip-Flop Scan Design .....6-5

Clock Skew and Edge-Triggered Flip-Flop Scan .....6-7

Clocked LSSD Scan Flip-Flop Design6-8

Guidelines for Flip-Flop Scan Design ......6-10

Scan Path Loading on Critical ac Path ....6-11

Bus Contention and Scan Testing ....6-12

Test-Isolation Modules6-14

Where Scan Is Not Efficient.6-20

7 IEEE Standard 1149.1-1990 7-1

Overview..7-2

Boundary-Scan Architecture .7-3

8 Generic Test Access Port 8-1

Overview..8-2

Test Register....8-3

Test Register—Bit Definitions .....8-5

Controller ..8-7

Communication Protocol 8-8

9 Parallel Module Test 9-1

Parallel Module Test of MegaModules9-2

MegaModule Test Collar.9-4

Single MegaModule PMT I/O Hookup 9-5

PMT Test Bus ..9-6

Multiple MegaModule PMT I/O Hookup.....9-7

PMT for Analog MegaModules ....9-9

In-System Use .....9-21

10 Parametric Measurements 10-1

Overview.10-2

Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type) ....10-4

Output Voltage Levels (DC_PARA TDL Type) .....10-10

Three-State High-Impedance Measurements (DC_PARA TDL Type) ...10-11

Input Current Measurements (DC_PARA TDL Type) .10-12

Quiescent Drain Supply Current (IDDQ TDL Type) ....10-13

11 Automatic Test Pattern Generation 11-1

Introduction to Automatic Test Pattern Generation 11-2

Path Sensitization 11-5

Full-Scan Designs ......11-6

Partial-Scan Designs ..11-7

Testing and Debugging Considerations ...11-8

Common ATPG Constraints 11-9

Summary .....11-10

12 Test Pattern Generation 12-1

Introduction to Testing 12-2

Test Pattern Creation..12-6

TDL Overview....12-13

13 IEEE Standard 1149.1-Based dc Parametric Testing 13-1

Introduction....13-2

Boundary-Scan Architecture .....13-3

Parametric Measurements Using Boundary-Scan Architecture ......13-10

Integrating Boundary-Scan Architecture and GTAP ...13-18

14 Military ASIC 14-1

Military-Specific Design Information .14-2

Military ASIC Topics Cross-Reference ....14-3

Glossary 1

Index Index-1