A CPLD VHDL Introduction

A CPLD VHDL Introduction

This introduction covers the fundamentals of VHDL as applied to Complex Programmable

Logic Devices (CPLDs). Specifically included are those design practices that translate soundly to CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.

VHDL, an extremely versatile tool developed to aid in many aspects of IC design, allows a user

to structure circuits in many levels of detail. This versatility also makes the job of the VHDL

synthesis tool a lot more complex, and there is latitude for interpretation depending on the

VHDL coding style. One synthesis tool may implement the same code very differently from

another. In order to achieve the best results using VHDL, the designer should work at the

Register Transfer Level (RTL).

Although working at the RTL for designs may be more time-consuming, all major synthesis

tools on the market are capable of generating a clear cut implementation of designs for CPLDs

at this level. Using higher levels of abstraction may give adequate results, but tend to be less

efficient. Additionally, by expressing designs in this manner, the designer also gains the ability

to port VHDL designs from one synthesis tool to another with minimal effort. The following

examples will show designers the best design practices when targeting Xilinx XC9500XL,

XC9500XV and CoolRunnerTM XPLA3 families.

This application note covers the following topics: