HFAN-04.5.5评估电源噪声抑制比对PLL时钟合成器的

HFAN-04.5.5评估电源噪声抑制比对PLL时钟合成器的影响

Characterizing Power-Supply Noise RejecTIon in PLL Clock Synthesizers

This applicaTIon note discusses the effects of powersupply

noise interference on PLL-based clock

generators. It describes several measurement

techniques for evaluaTIng the resulTIng DJ

(deterministic jitter). Relationships are derived

outlining how frequency-domain spur measurements

can be used to evaluate timing jitter behavior.

Laboratory bench-test results are used to compare

the approaches, and demonstrate how to reliably

assess the PSNR (power-supply noise rejection)

performance of a reference clock generator