奇数次分频器

module count(out,clk,clr);parameter N=5;output out; input clk,clr;reg out1,out2;reg [N/2:0] count1,count2;always @(posedge clk or posedge clr ) if(clr) begin count1=0; out1=0; end else begin count1 = count1 + 1; if( count1 == ((N