串并转换VHDL代码

通过多通道串-并转换器将多个同步串行数据流转换为并行数据 xilinx提供

Synthesis

 1. Launch synplify

 2. Correct the source file pathname in the encoder_1553.prj

 3. Open project /1553_enc_dec/synthesis/EC/synplify/encoder_1553.prj

 4. Click [Run]

Place and Route

 1. Launch ispLEVER

 2. Open project "/1553_enc_dec/par/EC/encoder_1553.syn"

 3. Click "Place and Route Trace Report" on right pannel