UART VHDL程序说明和时序图

The use of hardware descripTIon language (HDL) is becoming a more dominant factor, when designing

and verifying FPGA designs. The use of behavior level descripTIon not only increases the design

producTIvity, but also provides unique advantages in the design verificaTIon. The most dominant HDLs

today are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and

verification of a digital UART (Universal Asynchronous Receiver & Transmitter).