10bitADC_lifule.m

The Pipelined ADC is a practical and efficient structure for moderate speed(1-200MS/s), moderate resolution (10-16 bits) ADCs. Below is a Simulink model for a pipelined ADC including non-idealities such as offsets, matching, and noise. The model resolution is very flexible, and system level techniques are easily added. A matlab script for processing the data is also included. pipelined_adc_model.mdl pipelined_adc_model_testscript.m The MDAC One of the major components in the pipeline ADC has traditionally been the Multiplying Digital to Analog Converter (MDAC). This unit preforms the subtraction, DAC, and residue multiplication of a typical pipeline stage. Shown below is an example 1.5 bit DAC: