\Hardware_Verification_With_SystemVerilog(May_2007)[1]

Verification through inspection There are similarities with the development of OOP and that of functional verification, and while hardware verification is a younger field than software programming, it has (not surprisingly) followed a similar path. As readers of this handbook surely know, functional verification has come a long way from its recent humble beginning as a (mostly manual) process of verifying simulation waveforms. From there, it evolved into “golden” files; a current simulation run was compared to a known-to-begood result file—the golden file. For this technique to work it required fixed stimuli, often provided in simple text format. Golden files were an acceptable technique for small designs, where the complete design could be tested exhaustively through a few simulation runs.