SYSTEMVERILOG FOR VERIFICATION
This book is the first one you should read to learn the SystemVerilog verification language constructs. It describes how the language works and includes many examples on how to build a basic coverage-driven, constrained-random layered testbench using Object-Oriented Programming (OOP). The book has many guidelines on building testbenches, which help show why you want to use classes, randomization, and functional coverage. Once you have learned the language, pick up some of the methodology books listed in the References section fo r more information on building a testbench.
用户评论
还不错,很清楚,不是扫面版的
还不错 可惜不是最新版本