电源技术中的格雷码计数器用vhdl怎样实现?

variable count:std_logic_vector(3 downto 0); if clk'event and clk='1' then case count is when "0000"=>count:="0001"; when "0001"=>count:="0011"; when "0011"=>count:="0010"; when "0010"=>count:="0110"; when "0110"=>count:="0111"; when "01