EDA/PLD中的格雷码转自然码的VHDL实现

library IEEE;use IEEE.std_logic_1164.all;entity grey2norm is generic (width: integer := 8); port ( grey: in std_logic_vector(width - 1 downto 0); norm: out std_logic_vector(width - 1 downto 0) ); end grey2norm; architecture behav of grey2norm i