理解时钟抖动对高速ADC的影响

抖动对ADC性能产生的影响是由输入频率而不是采样率产生。时钟源的选择由应用需求决定。尽量用ADC评估板对时钟源进行测试，而不是相信时钟厂商的说法。advertisementUnderstandingtheEffectofClockJitteronHighSpeedADCsDesignNote1013DerekRedmayne(LTCApplicationsEngineer),EricTrelewicz(LTCApplicationsManager)andAlisonSmith(HighSpeedADCProductMarketingEngineer)Digitizinghighspeedsignalstoahighresolutionrequirestone,oranarrowband,withequivalentpowerat1MHz.carefulselectionofaclockthatwillnotcompromisetheTherearevariouscontributorstojitterinanyscenario,samplingperformanceoftheAnalogtoDigitalConverterextendingfromtheoscillatortoanyfrequencydividers,(ADC).Inthisarticleweh