AD转换控制模块.txt

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADZHKZ IS PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); RST:IN STD_LOGIC; CLK:IN STD_LOGIC; EOC:IN STD_LOGIC; ALE:OUT STD_LOGIC; START:OUT STD_LOGIC; OE:OUT STD_LOGIC; ADDA:OUT STD_LOGIC; BCDOUT: OUT STD_LOGIC