十位计数器 verilog程序
modulecount10(cin,clk,cout,qout);
inputcin,clk;
output[3:0]qout;
outputcout;
reg[3:0]qout;
always@(posedgeclk)
begin
if(cin)
begin
if(qout[3:0]==9)qout[3:0]=0;
elseqout[3:0]=qout[3:0]+1;
end
end
assigncout=((qout[3:0]==9)&cin)?1:0;
endmodule
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