10进制计数器VHDL代码
10进制计数器VHDL代码
LibraryIEEE;
UseIEEE.STD_LOGIC_1164.ALL;
UseIEEE.STD_LOGIC_UNSIGNED.ALL;
entitycounter_10is
Port(reset:instd_logic;
clock:instd_logic;
num_out:outstd_logic_vector(3downto0)
);
endcounter_10;
architectureBehaviorofcounter_10is
signaltemp:std_logic_vector(3
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