Configuration and Readback of Virtex FPGAs Using JTAG BoundaryScan
TheIEEE1149.1TestAccessPort(TAP)andBoundary-Scanarchitecture,commonlyreferredtoasJTAG,isapopulartestingmethod.JTAGisanacronymfortheJointTestActionGroup,thetechnicalsubcommitteeinitiallyresponsiblefordevelopingthestandard.Thisstandardprovidesameansto
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