四位全加器verilog代码

`timescale1ns/1nsmodulefulladd_4(sum,c_out,a,b,c_in);output[3:0]sum;outputc_out;input[3:0]a,b;inputc_in;wirep0,g0,p1,g1,p2,g2,p3,g3;wirec4,c3,c2,c1;........................