I2C控制器的Verilog源程序下载

The I

2

C bus provides a simple two-wire means of communicaTIon. This protocol is used in many applicaTIons.

SDRAM modules implement a serial EEPROM that supports the I

2

C protocol. This is used so that a microprocessor

can read the EEPROM for configuraTIon purposes.

This reference design documents an I

2

C Controller designed to interface with serial EEPROM devices. It is

intended to be a simple controller providing random reads cycles only. Typically, serial EEPROMs are programmed

at board assembly TIme and store configuration information, which is read by a microprocessor during power-up.

This design was implemented in Verilog, synthesized and fitted using Lattice’s ispDesignEXPERT™ software into a

ispMACH™ 4A device. The design requires 46 macrocells and 24 I/O pins. Using an M4A-64/32-55 yields greater

than 153MHz performance. Results may vary according to the synthesis tool.

This design assumes the user has experience with I

2

C controllers. Information available in documents listed in the

Applicable Documents section, below, is not repeated in this document