74197 TTL 二进制可预置锁存器、计数器

The '197 ripple counter contains divide-by-two and divideby-

eight sections which can be combined to form a modulo-

16 binary counter. State changes are initiated by the falling

edge of the clock. The '197 has a Master Reset (MR) input

which overrides all other inputs and asynchronously forces

all outputs LOW. A Parallel Load input (PL) overrides

clocked operations and asynchronously loads the data on

the Parallel Data inputs (Pn) into the flip-flops. This preset

feature makes the circuit usable as a programmable counter.

The circuit can also be used as a 4-bit latch, loading

data from the Parallel Data inputs when PL is LOW and

storing the data when PL is HIGH.