Power-constrained Testing of V

Increased levels of chip integraTIon combined with physical limitaTIons of heat

removal devices, cooling mechanisms and battery capacity, have established

energy-efficiency as an important design objecTIve in the implementaTIon flow of

modern electronic products. To meet these low energy objectives, new low

power techniques, including circuits, architectures, methodologies, algorithms

and computer-aided design tool flows, have emerged.

If the integration trend continues in the coming decade, i.e. transistors on lead

microprocessors double every two years, die size grows by 14% every two years,

supply voltage scales meagerly, and frequency doubles every two years, then

what would happen to power and energy? Expected power consumption of such

microprocessors, which goes beyond 100watts today, will grow by an order of

magnitude every two years reaching 10Kwatts in 2008. It is clear that excessive

power usage may become prohibitive and total power consumption will be a

limiting factor in the near future. These two factors will become even more

critical for lower performance applications, such as in portable products, where

low power techniques becomes a necessity. Planning for power need to be

incorporated into the design flow of such systems.

Since most of the existing low power techniques aim to reduce the switching

activity during the functional operation, they may conflict with the state-of-theart manufacturing test flow.

In fact, power management is not limited to the design space only, testing chips

with high power consumption is a major problem too. For example, a complex

chip may consume three or four times higher power during testing when

compared to its functional operation. This leads to a reliability problem since

overheating can cause destructive test. An additional concern for testing low

power circuits is caused by the interaction between the existing design-for-test

methods and voltage drop on power/ground networks. Due to high circuit

activity when employing scan or built-in self-test, the voltage drop which occurs

only during test will cause some good circuits to fail the testing process, thus

leading to unnecessary manufacturing yield loss. Therefore, accounting for

power dissipation during test is emerging as a necessary step in the

implementation flow, which will ultimately influence both the quality and the

cost of test. To keep the pace with the low power design practices, it is essential that the emerging system-on-a-chip test methodologies regard power-constrained testing as an important parameter when establishing the manufacturing test requirements. Today, we have started to see certain embedded test solutions that are designed with infrastructure IP to perform power management on-chip. With

the increasing use of embedded cores from third party IP providers, it is expected

that power-constrained test solutions be implemented at the cores level by the

third party IP providers.

This book is the first comprehensive book that covers all aspects of powerconstrained test solutions. It is a reflection of authors’ own research and also a survey of the major contributions in this domain. I strongly recommend this book to all engineers involved in design and test of system-on-chip, who want to

understand the impact of power on test and design-for-test.