ASIC to FPGA 设计方法和指导

ASIC to FPGA设计方法和指导ASIC to FPGADesignMethodology and GuidelinesOctober2007,ver.2.0Application Note311Introduction The cost of designing ASICs is increasing every year.In addition to the non-recurring engineering(NRE)and mask costs,development costs are increasing due to ASIC design complexity.Issues such as power,signal integrity,clock tree synthesis,and manufacturing defects can add significant risk and time-to-market delays.FPGAs offer a viable and competitive option to ASIC development by reducing the risk