Advanced ASIC Chip Synthesis U

UNIX is a registered trademark of UNIX Systems Laboratories, Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

RSPF and DSPF is a trademark of Cadence Design Systems, Inc.

SDF and SPEF is a trademark of Open Verilog International.

Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! are

registered trademarks of Synopsys, Inc.

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