验证方法手册的SystemVerilog

When VHDL first came out as an IEEE standard, it was thought to be sufficient to

model hardware designs. Reality proved to be a little different. Because it did not

have a predefined four-state logic type, each simulator and model vendor had to

create its own—and incompaTIble—logic type. This situaTIon prompted the quick

creaTIon of a group to create a standard mulTI-valued logic package for VHDL that

culminated with the 1164 standard. With such a package, models became

interoperable and simulators could be optimized to perform well-defined operations.

The authors of this book hope to create a similar standard for verification components

within the SystemVerilog language. The infrastructure elements specified in the

appendices can form the basis of a standard verification interface. If model vendors

use it to build their verification components, they will be immediately interoperable.

If simulator vendors optimize their implementation of the standard functions, the

runtime performances can be improved.