VHDL Library of Arithmetic Uni

VHDL Library of Arithmetic Units fdl

A comprehensive library of arithmetic units written in synthesizable VHDL code has been

developed. The library contains components for a variety of arithmetic operations and for

different speed requirements. The library components are implemented as circuit generators

in parameterized structural VHDL code. Their modular and well-documented source code

allows for simple usage and easy customization. Highly efficient circuit architectures are

used, which are optimized for synthesis and cell-based design. In particular, the implemented

adder architectures are more flexible and have better performance than the ones typically used

in commercial products. This public domain VHDL library is platform independent, and it

provides circuits with comparable performance, but higher flexibility and a larger diversity

of arithmetic operations compared to commercial data path libraries.