Fast, Efficient and Predictabl

The influence of embedded systems is constantly growing. Increasingly powerful

and versaTIle devices are being developed and put on the market at a fast

pace. The number of features is increasing, and so are the constraints on

the systems concerning size, performance, energy dissipaTIon and TIming predictability.

Since most systems today use a processor to execute an applicaTIon

program rather than using dedicated hardware, the requirements can not be

fulfilled by hardware architects alone: Hardware and software have to work

together in order to meet the tight constraints put on modern devices. This

work presents approaches that target the software generation process using an

energy and memory architecture aware C-compiler. The consideration of energy

dissipation and of the memory architecture leads to a large optimization

potential concerning performance and energy dissipation.

This work first presents an overview over the used timing, energy and

simulation models for one processor architecture and for different memory

architectures like caches, scratchpad memories and main memories in both

SRAM, DRAM and Flash technology. Following an introduction to the used

compilation framework, the compiler based exploitation of partitioned scratchpad

memories is presented. A simple formalized Base model is presented that

models the consequences of statically allocating instructions and data to several

small scratchpad partitions, followed by a number of extensions that treat

memory objects and their dependencies at a finer granularity. A method for

allocating objects to separate scratchpad memories for instructions and data,

as found in the most recent ARM designs, is also presented. Finally, a model

that also considers the leakage power of memories is introduced. Results show

that significant savings of up to 80% of the total energy can be achieved

by using the presented scratchpad allocation algorithms. The flexibility and

extensibility of the presented approaches is another benefit.

Many embedded systems have to respect timing constraints. Therefore,

timing predictability is of increasing importance. Whenever guarantees concerning

reaction times have to be given, worst case execution time (WCET)

analysis techniques are being used during the design of the system in order