Parallel Scalable LDPC Archite

Low-density Parity Codes are gaining increasing popularity for error detection in communicaTIon systems due to their high performance and simplicity of implementaTIon. The objecTIve of this project is to design and implement a LDPC decoder with opTImized tradeoff between speed and area (hardware requirements). The decoder should be able to decode a (1020,510,3,6) code. Having the flexibility to work for other code rates is desirable. The decoder is based on the Belief Propagation Algorithm that calculates the log-likelihood values of the received signals and then iteratively updates the checknode and bitnode values to make a final hard decision on the received bits at the end of q iterations. This project implements only one iteration stage used in the above decoding process. Each iteration requires the following computations:

1) For each checknode j, calculates the sum of the incoming values

2) The Lcb values are then calculated as

3) The Lbc value for each bit node i, is given by