Verilog语法下载

Synthesizable Verilog is a subset of the full Verilog HDL [9] that lies within

the domain of current synthesis tools (both RTL and behavioral).

This document species a subset of Verilog called V0.1 This subset is intended

as a vehicle for the rapid prototyping of ideas.

The method chosen for developing a semanTIcs of all of synthesizable Verilog

is to start with something too simple { V0 { and then only to make it more

complicated when the simple semanTIcs breaks. This way it is hoped to avoid

unnecessary complexity. It is planned to dene sequence of bigger and bigger

subsets (V1, V2 etc.) that will converge to the version of Verilog used in the

VFE project2 at Cambridge.