UART 4 UART参考设计，Xilinx提供VHDL代码

UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl

This zip file contains the following folders:

 \vhdl_source  -- Source VHDL files:

     uart.vhd  - top level file

     txmit.vhd - transmit portion of uart

     rcvr.vhd -  - receive portion of uart

\vhdl_testfixture  -- VHDL Testbench files. This files only include the testbench behavior, they

        do not instantiate the DUT. This can easily be done in a top-level VHDL

         file or a schematic. This folder contains the following files:

     txmit_tb.vhd  -- Test bench for txmit.vhd.

     rcvr_tf.vhd  -- Test bench for rcvr.vhd.