PCIe_blk_plus_ug341_v1.14

Xilinx FPGA PCIe核用户手册1.14版本。The Endpoint Block Plus core internally instances the Virtex-5 Integrated Endpoint Block. See UG197, Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide for information about the internal architecture of the block. The integrated block follows the PCI Express Base Specification layering model, which consists of the Physical, Data Link, and Transaction Layers.