eetop.cn_synopsys_timing_constraint_and_optimiaztion.pdf

Synopsys Design Constraints (SDC) is a format used to specify the design intent, including the timing, power, and area constraints for a design. SDC is based on the tool command language (Tcl). The Synopsys Design Compiler, IC Compiler, and PrimeTime tools use the SDC description to synthesize an