microarchitecture.pdf

Contents 1 Introduction.......................................................................................................................3 1.1 About this manual.......................................................................................................3 1.2 Microprocessor versions covered by this manual........................................................4 2 Out-of-order execution (All processors except P1, PMMX)................................................5 2.1 Instructions are split into uops.....................................................................................5 2.2 Register renaming......................................................................................................6 3 Branch prediction (all processors).....................................................................................7 3.1 Prediction methods for conditional jumps....................................................................7 3.2 Branch prediction in P1.............................................................................................13 3.3 Branch prediction in PMMX, PPro, P2, and P3.........................................................17 3.4 Branch prediction in P4 and P4E..............................................................................18 3.5 Branch prediction in PM and Core2..........................................................................21 3.6 Branch prediction in AMD64.....................................................................................22 3.7 Indirect jumps (all processors except PM and Core2)...............................................25 3.8 Returns (all processors except P1)...........................................................................25 3.9 Static prediction........................................................................................................26 3.10 Close jumps......................................................................