verilog程序------逻辑门

FPGA入门实验程序 module gates1( input wire[4:1]x, output wire[6:1]z ); assign z[6]=&x; assign z[5]=~&x; assign z[4]=|x; assign z[3]=~|x; assign z[2]=^x; assign z[1]=~^x; endmodule