library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder_38 is port( A2,A1,A0,S1,S2_L,S3_L:in std_logic; F_L:out std_logic_vector(0 to 7)); end decoder_38; architecture decoder_38p of decoder_38 is signal F_s :std_logic_vector(0 to 7); signal A :std_logic_vector(2 downto 0); begin A
