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Vice President and Editorial Director: Marcia J. Horton Senior Specialist, Program Planning and Support Executive Editor: Matt Goldstein Maura Zaldivar-Garcia Editorial Assistant: Kelsey loanes Cover Designer: Joyce Wells VPof Marketing: Christy Lesko Manager, Rights Management: Rachel Youdelmar Director of Field Marketing: Tim Galligan Associate Project Manager, Rights Management: Product Marketing Manager: Bram van Kempen William J. Opaluch c Field Marketing Manager: Demetrius Hall Full-Service Project Management: Paul Anagnostopoulos, Marketing Assistant: Jon Bryant Windfall Software Director of Product Management: Erin Gregg Composition: Windfall Software Team Lead Product Management: Scott Disanno Printer/Binder: Courier Westford Program Manager: Joanne Manning Cover Printer: Courier Westford Procurement Manager: Mary Fischer Typeface: 10/12 Times 10, ITC Stone Sans The graph on the front cover is a"memory mountain "that shows the measured read throughput of an Intel Core i7 processor as a function of spatial and temporal locality Copyright o 2016, 2011, and 2003 by Pearson Education, Inc. or its affiliates. All Rights Reserved. Printed in the United States of America. This publication is protected by copyright, and permission should be obtained from the publisher prior to any Pr d reproduction, storage in a retrieval sy stem, or transmission in any form or by any means, electronic, mechanical photocopying, recording, or otherwise. For information regarding permissions, request forms and the appropriate contacts withinthePearsonEducationgLobalRights&Permissionsdepartmentpleasevisitwww.pearsoned.com/permissions/ Many of the designations by manufacturers and seller to distinguish their products are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed in initial caps or all caps. The author and publisher of this book have used their best efforts in preparing this book. These efforts include the development, research, and testing of theories and programs to determine their effectiveness. The author and publisher make no warranty of any kind, expressed or implied, with regard to these programs or the documentation contained in this book. The author and publisher shall not be liable in any event for incidental or consequential damages with, or arising out of, the furnishing, performance, or use of these programs. Pearson Education Ltd., London Pearson Education Singapore, Pte. Ltd Pearson education Canada Inc Pearson Education--Japan Pearson Education Australia PTY. Limited Pearson Education North Asia, Ltd, Hong Kong Pearson educacin de mexico. S.A. de C.v. Pearson Education Malaysia, Pt Pearson Education, Inc, Upper Saddle river, New Jersey Library of Congress Cataloging-in-Publication Data Computer systems: a programmer's perspective/Randal e. Bryant, Carnegie Mellon University, David R O'Hallaron Bryant, Randle Carnegie Mellon University.-Third edition pages cm Includes bibliographical references and ine ISBN978-0-13-409266-9ISBN013409266X 1. Computer systems. 2. Computers. 3. Telecommunication. 4. User interfaces(Computer systems)I O'Hallaron, DavidR ( David Richard) II. Title. QA765.B795201 2015000930 0053-dc23 98765432 PEARSON ISBN10:0-13-409266 BN13:978-0-13-409266-9 To the students and instructors of the 15-213 course at Carnegie Mellon University, for inspiring us to develop and refine the material for this book MasteringEngineering For Computer Systems: A Programmer's perspective, third edition Mastering is Pearson's proven online Tutorial Homework program, newly available with the third edition of Computer Systems: A Programmer's Perspective. The Mastering platform allows you to integrate dynamic homework--with many problems taken directly from the Bryant/O'Hallaron textbook-with automatic grading. Mastering allows you to easily track the performance of your entire class on an assignment-by-assignment basis, or view the detailed work of an individual student Formoreinformationorademonstrationofthecoursevisitwww.Masteringengineering.com or contact your local Pearson representative Contents Preface xix about the authors xxxv A Tour of Computer Systems 1 1.1 Information Is Bits Context 3 1.2 Programs Are Translated by Other Programs into Different Forms 4 13 It Pays to Understand How Compilation Systems Work 6 1.4 Processors Read and Interpret Instructions Stored in Memory 7 1.4.1 Hardware Organization of a system 8 1.4. 2 Running the hello Program 10 1.5 Caches Matter 11 1.6 Storage Devices Form a hierarchy. 14 1.7 The Operating System Manages the Hardware 14 1.7.1 Processes 15 1.7.2 Threads 17 1.7.3 Virtual Memory 18 1.7.4 Files 19 18 Systems Communicate with other Systems using Networks 19 19 Important Themes 22 1.9.1 Amdahl's Law 22,) 1.9.2 Concurrency and Parallelism 24 1.9.3 The Importance of Abstractions in Computer Systems 26 1.10 Summary 27 Bibliographic Notes 28 Solutions to practice problems 28 Part I Program Structure and Execution Representing and manipulating information 31 2.1 Information Storage 34 2.1.1 Hexadecimal Notation 36 2.1.2 Data Sizes 39 vii Contents 2.1.3 Addressing and Byte Ordering 42 2.1.4 Representing Strings 49 2.1.5 Representing Code 49 2.1.6 Introduction to Boolean Algebra 50 2.1.7 Bit-Level Operations inC 54 2.1.8 Logical Operations in C 56 2.1.9 Shift Operations inC 57 22 Integer Representations 59 2.2.1 Integral Data Types 60 2.2.2 Unsigned Encodings 62 2.2.3 Two's- Complement Encodings, 64 2.2.4 Conversions between Signed and Unsigned 70 2.2.5 Signed versus Unsigned in C 74 2.2.6 Expanding'the Bit Representation of a Number 76 2.2.7 Truncating Numbers 81 2.2.8 Advice on Signed versus Unsigned 83 2.3 Integer Arithmetic 84 2.3.1 Unsigned Addition 84 2.3. 2 Two's-Complement Addition 90 2.3.3 Two's-Complement Negation 95 2.3.4 Unsigned Multiplication 96 2.3.5 Two,s-Complement Multiplication 97 2.3.6 Multiplying by Constants 101 2.3. 7 Dividing by Powers of 2 103 2.3.8 Final Thoughts on Integer Arithmetic 107 2.4 Floating Point 108 2.4.1 Fractional Binary Numbers 109 2.4.2 IEEE Floating-Point Representation 112 2.4.3 Example Numbers 115 2.4.4 Rounding 120 2.4.5 Floating-Point Operations 122 2.4.6 Floating Point in C 124 2.5 Summary 126 Bibliographic Notes 127 Homework Problems 128 Solutions to Practice Problems 143 Machine-Level Representation' of Programs 163 3.1 A Historical Perspective 166 Contents ix 3.2 Program Encodings 169 3.2.1 Machine-Level Code 170 3.2.2 Code Examples 172 3. 2. 3 Notes on Formatting 175 3.3 Data Formats 177 3.4 Accessing Information 1 79 3.4.1 Operand Specifiers 180 3.4.2 Data Movement Instructions. 182 3. 4.3 Data Moyement Example 186 3.4.4 Pushing and Popping Stack Data 189 3.5 Arithmetic and Logical Operations 191 3.5.1 Load Effective Address 191 3.5.2 Unary and Binary operationsr 194 3.5.3 Shift Operations 194 3.5.4 Discussion, 196 3.5.5 Special Arithmetic Operations 197 3.6 Control 200 3.6.1 Condition Codes 201 3. 6. 2 Accessing the Condition Codes 202 .t 5I 3.6.3 Jump Instructions 205 3.6.4 Jump Instruction Encodings 207 3.6.5 Implementing Conditional Branches with Conditional-Control 209 3.6.6 Implementing-Conditional Branches with Conditional Moves 214 3.6.7 Loops220 3.6.8 Switch Statements 232 3.7 Procedures 238 3.7.1 The Run-Time Stack 239 3.7.2 Control Transfer 241 3.7.3 Data Transfer 245 3.7.4 Local Storage on the Stack 248 3.7.5 Local Storage in Registers 251 3.7.6 Recursive Procedures 253 3.8 Array Allocation-and Access 255 3.8.1 Basic Principles 255 3.8.2 Pointer Arithmetic 257 3.8.3 Nested Arrays 258 3.8.4 Fixed-Size arrays 260 3.8.5 Variable-Size arrays 262 Contents 3.9 Heterogeneous Data Structures 265 3.9.1 Structures 265 3.9.2 Unions 269 3.9.3 Data Alignment 273 3.10 Combining Control and Data in Machine- Level Programs 276 3. 10.1 Understanding Pointers 277 3.10.2 Life in the Real World: Using the gdb Debugger 279 3.10.3 Out-of-Bounds Memory References and Buffer Overflow 279 3.10.4 Thwarting Buffer Overflow Attacks 284 3.10.5 Supporting Variable-Size Stack Frames 290 Floating-Point Code 293 3. 11.1 Floating-Point Movement and Conversion Operations 296 3. 11.2 Floating-Point Code in Procedures 301 3. 11.3 Floating-Point Arithmetic Operations 302 3. 11.4 Defining and Using Floating- Point Constants 304 3. 11.5 USing Bitwise Operations in Floating- Point Code 305 3. 11.6 Floating-Point Comparison Operations 306 3. 11.7 Observations about Floating-Point Code 309 3.12 Summary 309 Bibliographic Notes 310 Homework Problems 311 Solutions to practice Problems 325 Processor Architecture 351 4.1 The Y86-64 Instruction Set Architecture 355 4.1.1 Programmer-Visible State 355 4.1.2 Y86-64 Instructions 356 4.1.3 Instruction Encoding 358 4. 1. 4 Y86-64 Exceptions 363 4.1.5 Y86-64 Programs 364 4.1.6 Some Y86-64 Instruction Details 370 4.2 Logic Design and the Hardware Control Language HCL 372 4.2.1 Logic Gates 373 4.2.2 Combinational Circuits and HCL Boolean Expressions 374 4.2, 3 Word-Level Combinational Circuits and HCl Integer Expressions 376 4.2.4 Set Membership 380 4.2.5 Memory and Clocking 381 4.3 Sequential Y86-64 Implementations 384 4.3.1 Organizing Processing into Stages 384 contents xi 43.2 SEQ Hardware Structure 396G) 4.3.3 SEQ Timing 400 43. 4 SEQ Stage Implementations 404 3/u 4.4 General Principles of Pipelining 412 4.4.1 Computational Pipelines 412- VI( . N 4.4.2 A Detailed Look at Pipeline Operation; 414 4.4.3 Limitations of Pipelining 416 4.4.4 r Pipelihingea System with Feedback 419 4.5 Pipelined y86-64 Implementations: '421 93,"Ie 4.5.1 SEQ+: Rearranging the Computation Stages" 421 4.5.2 Inserting Pipeline Registers 422 lfc 4.5.3 Rearranging and Relabeling Signals 426 4.5.4 Next PC Prediction 427 4.5.5 Pipeline hazards 429 4.5.6 Exception Handling 444 4.5.7 PIPE Stage Implementations 447 4.5.8 Pipeline Control logic 455 4.5.9- Performance Analysis-464 4.5.10 Unfinished Business 468 4.6 Summary 470 4.6.1 Y86-64 Simulators 472 Bibliographic Notes 473 Homework Problems 473 Solutions to Practice Problems 480 Optimizing Program Performance: 495 5.1 Capabilities and Limitations of Optimizing Compilers 498 5.2 Expressing Program Performance. 502 5.3 Program Example 504 5.4 Eliminating Loop efficiencies 508 5.5 Reducing Procedure Calls 512( 5.6 Eliminating Unneeded Memory References). 514 5.7 Understanding Modern Processors 517, 5.7.1 Overall Operation 518 5.7.2 Functional Unit Performance 523 5.7.3 An Abstract Model of Processor Operation 525 5.8 Loop Unrolling 531(4 5.9 Enhancing Parallelism 536 5.9.1 Multiple, Accumulators 536 5.9.2 Reassociation Transformation 541