Cotrex M3权威指南(英文)

This page intentionally left blank The definitive Guide to the ARM Cortex-M3 Joseph Yiu AMSTERDAM· BOSTON· HEIDELBERO· LONDON· NEW YORK OXFORD· PARIS· SAN DIEGO· SAN FRANCISCO SINGAPORE· SYDNEY· TOKYO ELSEVIER Newnes is an imprint of elsevier Newnes Newnes is an imprint of elsevier 30 Corporate Drive, Suite 400, burlington, Ma ol803, USA Linacre house. jordan hill. oxford oX2 8DP UK Copyright o 2007, Elsevier Inc. All rights reserved No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher Permissions may be sought directly from Elsevier's Science Technology Rights Department in Oxford, UK: phone: (+44)1865 843830, fax: (+44)1865 853333, E-mail: permissions@elsevier comYoumayalsocompleteyourrequestonlineviatheElsevierhomepage(http:elsevier.com),by selecting"Support Contact then Copyright and Permission"and then"Obtaining Permissions Recognizing the importance of preserving what has been written, Elsevier prints its books on acid-free paper whenever possible Library of Congress Cataloging-in-Publication Data (Application submitted. British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library ISBN:978-0-7506-8534-4 For information on all Newnes publications visitourwebsiteatwww.books.elsevier.com 08091011121310987654321 ypeset by Charon Tec Ltd(A Macmillan Company), Chennai, India www.charontec.com Printed in The United States of america Working together to grow libraries in developing countries www.elsevier.comwww.bookaid.o www ElSEVIER ]Nternational Sabre Foundation Table of Contents Foreword Preface ......... X/V Acknowledgments Terms and abbreviations XVI Conventions XVIll References. Chapter1- Introduction....,... What Is the arm cortex-M3 Processor? Background of arm and arm architecture a Brief history Architecture versions 1133468 Processor Naming.............6 Instruction Set Development The Thumb-2 Instruction Set Architecture (ISa) Cortex-M3 Processor Applications..........................10 Organization of This book Further readings Chapter2- Overview of the Cortex-M3..................13 Fundamentals 13 Registers......... 14 RO to r12: General-Purpose registers. ...............................................14 R13: Stack Pointers 垂·非垂 ····· 14 R14: The link register......... RI5: The program counter 15 Special registers Operation modes .......................................................................................16 The built-In Nested Vectored Interrupt controller 17 Nested Interrupt Support 18 Vectored Interrupt Support 18 Dynamic priority changes support....... .18 Reduction of Interrupt latency 18 Interrupt Maskin... .18 Table of Contents The Memory Map The bus interface... 20 The Memory Protection Unit...... .20 The Instruction set 20 Interrupts and Exceptions......... 音音香音音音 22 Debugging Support...... .24 Characteristics Summary...... 25 High performance∴. 25 Advanced Interrupt-Handling Features...........................25 Low Power Consumption........................26 System Features 26 Debug Supports....... 26 Chapter 3-Cortex-M3 Basics 29 Registers............ 29 General- Purpose registers ro-R7............... 29 General-Purpose registers r8-R12 29 Stack Pointer r13 Link register r1l4... 32 Program Counter r15 .33 pecial Registers... 3 Program Status Registers(Psrs 33 PRIMASK. FAULTMASK. and basePri registers 35 The Control register... ...136 Operation mode 37 Exceptions and Interrupts. ........................................................................................39 V ector tables∴ 40 Stack Memory operations 41 Basic operations of the stack 鲁垂音音音 41 Cortex-M3 Stack Implementation. The Two-Stack model in the cortex-M3 43 Reset sequence 44 Chapter4- Instruction sets......,...,...,...,......47 assembly basics 7 Assembler Language: Basic Syntax. ..............47 Assembler language: Use of suffixes 48 Assembler Language: Unified Assembler Language.............49 Instruction list ...................50 Unsupported Instructions 55 Instruction Descriptions. .......................................................................................57 Assembler Language: Moving Data 57 LDR and adr Pseudo instructions 60 Table of contents Assembler Language: Processing data 61 Assembler language: Combined Compare and Conditional branch:、∴... Assembler language: call and unconditional branch Assembler Language: Decisions and conditional branches .67 ...70 Assembler Language: Conditional Branches Using IT Instructions 71 Assembler language: Instruction Barrier and Memory Barrier Instructions.............72 Assembly Language: Saturation Operations........................173 Several useful instructions in the Cortex-M3 75 MSR and mrs 75 IF-THEN 76 CBZ and cbnz 77 SDIV and udIV.178 REV REVH and resh 78 RBIT 78 SXTB. SXTH. UXTB and UXTH 79 bfC and bfi 79 UBFX and sfx 79 LDRD and strd........80 TBB and TBH 80 Chapter5- Memory Systems............83 Memory System Features Overview 83 Memory Maps... ····· 83 Memory Access Attributes ...86 Default memory access permissions .88 Bit-Band operations 88 Advantages of Bit-Band Operations 92 Bit-Band o on of different data sizes Bit-Band Operations in C programs...................................95 Unaligned Transfers................................ 96 ExclusiV e accesses 8 Endian mode 100 Chapter6- Cortex-M3 Implementation Overview.........,......103 The Pipeline...... ...103 A Detailed Block Diagram.................................105 Bus Interfaces on the Cortex-M3 108 The I-Code bus 108 The D-Code bus ...................................................................................................108 The System bus The External Private Peripheral bus 109 The debug Access Port Bus....,.,,,...,...,109 Other Interfaces on the cortex-M3 Table of Contents The External Private Peripheral bus..................................................109 Typical Connections 111 Reset signals 112 Chapter 7-Exceptions 115 Exception Types......... ......115 Definitions of Priority. 117 V ector tables 123 Interrupt Inputs and Pending behavior.................................... 124 Fault exceptions 127 Bus faults ,127 Memory Management Faults............................ 129 Usage faults 130 Hard faults 132 Dealing with Faults...... 132 SVC and pendsv 133 Chapter 8-The NviC and Interrupt Control 137 NVIC Overview 137 The Basic Interrupt Configuration..........................................138 Interrupt enable and clear enable .138 Interrupt Pending and Clear Pending...... ...138 Priority Levels. 140 Active Status PRIMASK and FAULtmasK Special Registers 141 The basePrI Special Register..................................................................142 Configuration Registers for Other exceptions 143 Example Procedures of Setting Up an Interrupt ...144 Software Interrupts 146 The SYsticK Timer 147 Chapter9- Interrupt Behavior∴..............................149 Interrupt,/ Exception Sequences.................................... 149 Stacking.......................................... 149 V ector fetches 150 Register updates 151 Exception exits 151 Nested Interrupts 152 Tail-Chaining Interrupts 音音音 152 Late arrivals 153 More on the exception return value 153 Interrupt Latency......... 154 Faults related to Interrupts...... 156 Table of contents cking 156 Unstacking...... 157 Vector fetch 157 Invalid returns..................................157 Chapter 10-Cortex-M3 Programming 159 Overview 159 Using assembly. 159 Using C ...160 The Interface between assembly and c ...161 A Typical Development Flow............162 The First Step..................... ...162 Producing Outputs 164 The“ Hello world” Example.....................165 Using Data Memory...... 169 USing Exclusive Access for Semaphores ...170 USing Bit Band for Semaphores...........................72 Working with bit field extract and Table branch 173 Chapter 1 1-Exceptions Programming 175 Using Interrupts 175 Stack setup ......175 Vector Table Setup............... 176 Interrupt Priority Setup............ 177 Enable the Interrupt... ∴178 Exception/ Interrupt handlers...... ····· ,179 Software Interrupts... ...180 Example with exception handlers 181 USing Svo......... 184 SVC Example: Use for Output Functions 186 USing svc with c 189 Chapter 12- Advanced Programming features and System Behavior 193 Running a System with Two Separate Stacks ...193 Double- Word Stack Alignment.....,,...,.....................196 Nonbase thread enable 197 Performance Considerations 200 Lockup Situations....................................... 201 What Happens During Lockup? 201 Avoiding Lockup 202 Chapter 13-The Memory Protection Unit 205 Overview ...205 MPU Registers... 206