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Bringing Agile Methods Into Functional Verification

上传者: 2019-01-01 20:49:57上传 PDF文件 498.28KB 热度 35次
Agile Programming is a highly disciplined methodology used in software engineering. One aspect of the Agile methodology that is applicable to ASIC/FPGA functional verification and particularly important when creating verification environments using an Object Oriented paradigm is the Test Driven Development [2]. This process encourages the creation of a separate unit test for every critical class that is defined in a system. This paper describes the value of using a SystemVerilog unit test framework when creating a functional ver ification environment. Applying this Agile aspect may help achieve improvements in both quality and productivity. The usage model, the design of a unit test framework created for SystemVerilog (called svunit), and a concrete example of its usage are also presented. ification environment. Applying this Agile aspect may help achieve improvements in both quality and productivity. The usage model, the design of a unit test framework created for SystemVerilog (called svunit), and a concrete example of its usage are also presented.
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