xilinx sysgen tutorial

Xilinx Sysgen教程，很不错的资料，推荐学习！！Table of ContentsPreface: About This GuideGuide contents9System Generator PDF Doc setAdditional resourcesConventions∴.,,,,,,,,,,,10TypographOnline document10Chapter 1: Hardware Design Using System GeneratorA Brief Introduction to FPgas14ote to the dsp engineer18ote to the Hardware Engineer18Design Flows using System GeneratorAlgorithm ExplorationImplementing part of a larger designImplementing a Complete DesignSystem-Level modeling in System Generator20System generator blocksets21Signal Types23Bit-True and Cycle-True Modeling24Timing and Clocking.……...24Synchronization mechanisms36Block masks and Parameter Passing36Estimate39Automatic code generation39Compiling and Simulating Using the System Generator BlockViewing ISE Reports44Compilation results44HDL Testbench50Compiling MatlaB into an FPGA..51Simple selector,.··.······..········51Simple arithmetic Operations52Complex multiplier with latencyShift o56assing Parameters into the mCode blocktional Input ports60Finite State MachinesParameterizable accumulator63FIR Example and system verification...,.,,66RPN Calculator.......69Example of disp functionImporting a system Generator Design into a Bigger systemHDL Netlist Compilation73Integration Design RulesNew Integration Flow between System Generator Project Navigator74System Generator for dSP User Guidewww.xilinx.comUG640(v11. 4)December 2, 2009XLINⅩp-by-Step ExampleConfigurable Subsystems and System GeneratorDefining a Configurable SubsystemUSing a Configurable Subsystem,,,,,,,.84Deleting a block from a Configurable SubsystemAdding a Block to a Configurable SubsystemGenerating hardware from Configurable SubsystemsNotes for Higher Performance FPga designReview the Hardware Notes Included in Block Dialog BoxesRegister the inputs and outputs of your design..88Insert Pipeline registers,,,,,,,,,,88Use Saturation arithmetic and rounding only when necessaryUse the System Generator Timing and Power Analysis ToolsSet the Data Rate Option on All Gateway blocksReduce the clock enable(ce) FanoutProcessing a System Generator Design with FPGA Physical Design Tools.. 89HDL SimulationGenerating an FPGA BitstreamResetting Auto-Generated Clock Enable Logicce_clr and Rate Changing Blocks95ce clr Usage recommendationsDesign Styles for the DSP4898About the dsp4898Designs Using Standard ComponentsDesigns Using Synthesizable Mult, Mux and AddSub Blocks99Designs that Use DSP48 and DSP48 Macro BlocksDSP48 Design Techi.....105Using FDATool in Digital Filter Applications....·;····Design OverviewOpen and generate the coefficients for this FIr Filter.109Parameterize the mac-Based fir block110Generate and assign Coefficients for the FIr filter111Browse Through and Understand the xilinx Filter block113Run the simulation········:·····,,,,,,,,,,,,,,,,114Generating Multiple cycle-True Islands for Distinct Clocks117Multiple Clock Applications117Clock domain Partitioning.,,,,118Crossing Clock domainsNetlisting Multiple Clock Designs120Step-by- Step Example∴121Creating a Top-Level WrapperUsing Chip Scope Pro Analyzer for Real-Time Hardware DebuggingChipscope pro overview:·129Tutorial Example: Using ChipScope in System Generator129Real-Time DebugImporting Data Into the MATLAB Workspace From ChipScpe.鲁垂134..138Chapter 2: Hardware/Software Co-DesignHardware/Software Co-Design in System Generator140Black box block······..140Picoblaze block,,,,,,,,140www.xilinx.comSystem Generator for DSP User GuideUG640(v11.4 )December 2, 2009&A XILINXEDK Processor block140Integrating a Processor with Custom Logic140Memory Map ciHardware generation,,,,,,,,,,,,,,,,,,,,,,,,,,142Hardware Co-Simulation143Generating Software Drivers143Writing Software for EDK Processors144Asynchronous Support for EDK Processors......145EDK Support147Importing an EDK Processor,..147Exposing Processor Ports to System∈ enerator..∴…∴.....149Exporting a pcore...150Designing with Embedded Processors and microcontrollers150Designing PicoBlaze Microcontroller Applications,,150Designing and Exporting MicroBlaze Processor Peripherals,,,,,,,,157Tutorial Example - Designing and Simulating MicroBlaze Processor Systems... 162Using XPS∴∴170USing Platform Studio SDK175Chapter 3: Using Hardware Co-Simulation185M-Code Access to hardware co-simulation.185Installing Your hardware Platform···∴....185Ethernet-Based Hardware Co-Simulation185JTAG-Based Hardware Co-Simulation·番垂Third-Party Hardware Co-SimulationCompiling a Model for Hardware Co-Simulation187Choosing a Compilation Target187Invoking the Code generator187Hardware Co-Simulation blocks188Hardware Co-Simulation Clocking191Selecting the target Clock FrequencyockingModesSelecting the Clock Mode192Board-Specific 1/0 Ports..193I/O Ports in Hardware Co-simulation194Ethernet hardware Co-SimulationPoint-to-Point Ethernet hardware Co-Simulation194...195Network-Based Ethernet Hardware Co-SimulationShared Memory Support200Compiling shared memories for Hardware Co-Simulation201Co-Simulating Unprotected Shared Memories203Co-Simulating Lockable Shared memories204Co-Simulating Shared registersng206Co-Simulating Shared FIFOS207Restrictions on Shared memories210Specifying Xilinx Tool Flow Settings210Frame-Based Acceleration using Hardware Co-SimulationShared memories212Adding Buffers to a Design214System Generator for dSP User Guidewww.xilinx.comUG640(v11. 4)December 2, 2009XLINⅩCompiling for hardware co-simulation218Using Vector Transfers220Real-Time Signal Processing using Hardware Co-Simulation225Applying a 5x5 Filter Kernel Data Path2275x5 Filter Kernel test bench番鲁垂番番230Reloading the Kernel234Installing Your Hardware Co-Simulation Board235Installing an ml402 Platform for ethernet hardware co-simulation235Installing an ml506 Platform for Ethernet hardware Co-Simulation244Installing an ml605 Platform for Ethernet Hardware Co-Simulation253Installing a Spartan 3A DSP 1800A Starter platform for ethernet hardware co-simulation 257Installing a Spartan 3A DSP 3400A Development Platform for Ethernet hardware Co260Installing an ml402 Platform for TAG Hardware Co-Simulation269Installing an ml605 Platform for JTAG Hardwarc Co-Simulation271Installing an SP605 Platform for JTAG Hardware Co-Simulation273Supporting New Platforms through JTAG Hardware Co-Simulation275Hardware requirements275Supporting New Platforms275Chapter 4: Importing HDL ModulesBlack Box hdl requirements and restrictions290Black Box Configuration wizard.291Black box configuration m-functionHDL Co-Simulation303Introduction..303Configuring the hdl simulator303Co-Simulating multiple black Boxes.305Black Box Examples.306Importing a Xilinx Core Generator Module306Importing a VHDL Module.320Importing a Verilog Module327Dynamic black boxes..329Simulating several black boxes simultaneously....331Advanced Black Box Example Using ModelSim333Importing, Simulating, and Exporting an Encrypted VHDL FileChapter 5: System Generator Compilation TypesHDL Netlist Compilation∴…344NGC Netlist Compilation344Bitstream Compilation..345XFLOW Option FilesAdditional Settings347Re-Compiling EDK Processor Block Software Programs in Bitstreams348EDK Export Tool349Creating a Custom Bus Interface for Pcore export.,,...,,,,350Export as pcore to edK..,351System Generator Ports as Top-Level Ports in EDK352Supported Processors and Current Limitations352www.xilinx.comSystem Generator for DSP User GuideUG640(v11.4 )December 2, 2009&A XILINXSee alsHardware Co-Simulation Compilation.....353Timing and Power Analysis Compilation353Timing Analysis Concepts Review355Timing Analyzer Features356Creating Compilation Targets367Defining New Compilation TargetsInder373System Generator for dSP User Guidewww.xilinx.comUG640(v11. 4)December 2, 2009XLINⅩwww.xilinx.comSystem Generator for DSP User GuideUG640(v11.4 )December 2, 2009R XILINXPrefaceabout This guideThis User Guide provides in-depth discussions on topics that are key to understandingand using System generator. In addition, examples and turorials are also provided thatextend beyond the scope of the System Generator Getting Started guideGuide ContentsThis User Guide contains information the following topicsHardware Design using System GeneratorHardware Software Co-DesignHardware Co-SimulationImporting HDL ModulesSystem Generator Compilation TypesSystem Generator PDF Doc SetThis User Guide can be found in the System Generator Help system and is also part of theSystem Generator Doc Set that is provided in PDF format. The content of the doc set is asSysterm Generator for DSP Getting Started GuideSystem Generator for DSP User GuideSystem Generator for dSP Reference guideNote: Hyperlinks across these PdF documents work only when the Pdf files reside in the samefolder. After clicking a Hyperlink in the Adobe Reader, you can return to the previous page by pressingthe Alt key and the left arrow key (o at the same timeAdditional resourcesTo find additional documentation see the Xilinx website at:http://www.xilinx.com/support/documentation/index.htmTo search the Answer Database of silicon, software, and IP questions and answers, or tocreate a technical support Web Case, see the Xilinx website athttp://www.xilinx.com/support/mysupport.htmSystem Generator for dSP User Guidewww.xilinx.comUG640(v11. 4)December 2, 2009Preface: About this guideXLINⅩConventionsThis document uses the following conventions. An example illustrates each conventionTypographicalThe following typographical conventions are used in this documentConventionMeaning or useExampleCourier fontMessages,prompts,andspeed gradeprogram files that the systemdisplaysCourier boldLiteral commands that you ngdbuild design_namelenter in a syntactical statementHelvetica boldCommands that you select from File -Opena menuKeyboard shortcutsCtrl+CItalic fontVariables in a syntax statement ngabuild design_namefor which you must supplaliReferences to other manuals See the Development SystemReference guide for moreinformationEmphasis in textIf a wire is drawn so that itoverlaps the pin of a symbolthe two nets are not connectedquare brackets ] An optional entry or parameter. ngdbuild [option_nameHowever, in bus specifications design namesuch as bus [7: 01, they arerequiredBraces( JA list of items from which you lowpwr =fon off]must choose one or moreVertical barSeparates items in a list oflowpwr =ion offyoIcesVertical ellipsisRepetitive material that has IOB #1: Name= QOUTbeen omitted工OB#2:Name= CLKIN′Horizontal ellipsis .. Repetitive material that hasallow block block name loc1been omittedl0C2∴loc;Online documentThe following conventions are used in this document10www.xilinx.comSystem Generator for DSP User GuideUG640(v11.4 )December 2, 2009