USB OTG FPGA

USB OTG FPGA2015.05Supported PHYS18On the integration side, the USB OTG controller supports the following featuresDifferent clocks for system and PHy interfacesDedicated TX FIFO buffer for each device IN endpoint in direct memory access(DMa)modePacket based, dynamic FIFO memory allocation for endpoints for small FIFO buffers and flexible,efficient use of ram that can be dynamically sized by softwareAbility to change an endpoint's FIFO memory size during transfersClock gating support during USB suspend and session off modesPHY clock gating supportSystem clock gating supportData FIFO RAM clock gating supportLocal buffering with error correction code(eCC)supportNote: The USB OTG controller does not support the following protocolsEnhanced host Controller Interface(EHCIOpen Host Controller Interface(OHChUniversal Host Controller Interface(UHCISupported PHYsThe USB OTG controller only supports USB 2.0 ULPI PHYS. Only the single data rate(SDr)mode issupportedis recommended that designers use the MicroChip USB3300 PHY device that has been proven to be ue.ILPHYS that support LPM mode may not function properly with the USB controller due lo a Liming issuccessful on the development boardRefer to the cyclone v Device Datasheet for specific timing in formationUSB 2.0 OTG ControllerAltera CorporationSend FeedbackCV 5v418-4USB OTG Controller Block Diagram and System Integration2015.05.04USB OTG Controller Block Diagram and System IntegrationFigure 18-1: USB OTG Controller System IntegrationTwo subsystems are included in the hPsL3 InterconnectMasterSlaveInterfaceInterfaceIs ControstemManager ECC ControlUSB OTGControllerResetULPI PHYInterfaceExtemal USB transceiverThe USB Otg controller connects to the level 3(13)interconnect through a slave interface, allowingother masters to access the control and status registers(Csrs)in the controller. The controller alsoconnects to the L3 interconnect through a master interface, allowing the dma engine in the controller tomove data between external memory and the controllerA single port RAM (SPRAM)connected to the USB OTG controller is used to store USB data packets forboth host and device modes. It is configured as fiFO buffers for receive and transmit data packets on theUSB link.Through the system manager the usb otg controller has control to use and test error correction codes(ECCS)in the SPRAM. Through the system manager, the USB OTG controller can also control thebehavior of the master interface to the l3 interconnectThe USB OTG controller connects to the external usB transceiver through a ulpi phy interface. Thisinterface also connects through pin multiplexers within the HPS. The pin multiplexers are controlledthe system manageradditional connections on the usbotg controller includeClock input from the clock manager to the USB OtG controllerReset input from the reset manager to the uSb otg controllerInterrupt line from the USB OtG controller to the microprocessor unit(mpu) global interruptcontroller (gic)Altera CorporationUSB 2.0 OTG ControllerSend Feedback2015.05.04Functional Description of the USB OTG Controller18-5The usb controller will only use Direct Shared IO 48Related InformationSystem Manager on page 5-1Details available in the System Manager chapterGeneral-Purpose I/o Interface on page 22-1Functional Description of the USB OTG ControllerUSB OTG Controller block DescriptionFigure 18-2: USB OTG Controller Block DescriptionDetails about each of the units that comprise the USB OTG controller are shown belowL3 InterconnectUSB OTGControllerMaster interfaceSlave interfaceApplication Interface UrSPRAMPacket e|F0〔 ontrollerMedia access controllerWakeup and Phy controllerPHY InterfaceULP PHY InterfaceExternal USB transceiverMaster InterfaceThe master interface includes a built in dma controller. The dma controller moves data betweenexternal memory and the media access controller (mac)Properties of the master interface are controlled through the USB L3 Master HPROT Registerin the system manager. These bits provide access information to the l3 interconnect, including whetheror not transactions are cacheable, bufferable, or privilegedUSB 2.0 OTG ControllerAltera CorporationSend FeedbackCV 5v4186Slave Interface2015.05.04Note: Bits in theregister can be updated only when the master interface is guaranteed to be inan inactive stateSlave InterfaceThe slave interface allows other masters in the system to access the usb otg controller's csrs Fortesting purposes, other masters can also access the spramSlave Interface Csr UnitThe slave interface can read from and write to all the CSrs in the uSB otG controllers. All registeraccesses are 32 bitsThe csr is divided into the following groups of registersGlobalHostDevicePower and clock gatingSome registers are shared between host and device modes, because the controller can only be in one modeat a time The controller generates a mode mismatch interrupt if a master attempts to access deviceregisters when the controller is in host mode, or attempts to access host registers when the controller is indevice mode. Writing to unimplemented registers is ignored. Reading from unimplemented registersreturns indeterminate valuesApplication Interface UnitThe application interface unit(AlU)generates DMA requests based on programmable FIFO bufferthresholds. The aiu generates interrupts to the GiC for both host and device modes. A DMA scheduler isincluded in the alu to arbitrate and control the data transfer between packets in system memory andtheir respective USB endpointsPacket fifo ControllerThe Packet FIFO Controller(PFC)connects the AIU with the Mac through data Fifo buffers located inthe sPram. In device mode, one fifo buffer is implemented for each in endpoint In host mode, asingle FIFo buffer stores data for all periodic(isochronous and interrupt) OUT endpoints, and a singleFIFO buffer is used for nonperiodic(control and bulk) ouT endpoints. Host and device mode share asingle receive data Fifo bufferSPRAMAn SPRaM implements the data fifo buffers for host and device modes The size of the fifo buffers canbe programmed dynamicallyThe SPRAM supports ECCS ECCs can be enabled through the system manager, by seLling the RAM ECCEnable( )bit in the USBO or USBI RAM ECC Enable Register( or ) in the ECC ManagementRegister Group( ) Single bit and double bit errors in each USB instance can be injected using thisregisterAltera CorporationUSB 2.0 OTG ControllerSend Feedback2015.05MAC18-7The SPRaM provides outputs to notify the system manager when single bit correctable errors aredetected(and corrected), and when double bit(uncorrectable)errors are detected. The system managergenerates an interrupt to the GiC when an ECC error is detectedMACThe Mac module implements the following functionality:USB transaction supportHost protocol supportDevice protocol supportOTG protocol supportLink power management(LPM)functionsUSB TransactionsIn device mode, the mac decodes and checks the integrity of all token packets For valid out or setuptokens, the following DATA packet is also checked If the data packet is valid, the Mac performs thefollowing steps1. writes the data to the receive fifo buffer2. Sends the appropriate handshake when required to the usb hostIf a receive Fifo buffer is not available, the mac sends a nak response to the host. The mac alsosupports ping protocolFor iN tokens, if data is available in the transmit FIfo buffer, the mac performs the following steps1. Reads the data from the fifo buffer2. Forms the data packet3. Transmits the packet to the host4. Receives the response from the host5. Sends the updated status to the pfcIn host mode, the mac receives a token request from the AlU. The mac performs the following steps1. Builds the token packet2. Sends the packet to the deviceFor OUT or SETUP transactions, the MAC also performs the following steps1. Reads the data from the transmit fifo buffer2. Assembles the data packet3. Sends the packet to the device4. Waits for a responseThe response from the device causes the mac to send a status update to the aluUSB 2.0 OTG ControllerAltera CorporationSend FeedbackCV 5v418-8Host protocol2015.05.04For IN or PING transactions, the mac waits for the data or handshake response from the device For dataresponses, the Mac performs the following steps1. Validates the data2. writes the data to the receive fifo buffer3. Sends a status update to the alu4. Sends a handshake to the device, if approprialeHost ProtocoIn host mode, the MAC performs the following functionsDetects connect, disconnect, and remote wakeup events on the usB linknitrates resetInitiates speed enumeration processesGenerates Start of Frame(SOF)packetsDevice protocoIn device mode, the mac performs the following functionsHandles usb reset sequenceHandles speed enumerationDetects uSB suspend and resume activity on the usb linkInitiates remote wakDecodes SOF packetsOTG ProtocoThe MAC handles HNP and SRP for OTG operation. HNP provides a mechanism for swapping host anddevice roles. sRP provides mechanisms for the host to turn off VBus to save power, and for a device torequest a new USB sessionLPM FunctionsThe USB Otg controller supports LPM in both host and device modes. With this feature, the USB OTGcontroller can enter a sleep state when a successful LPM transaction occurs on the USB link.Wakeup and Power ControlTo reduce power, the USB OTG controller supports a power down mode In power down mode, thecontroller and the Phy can shut down their clocks. The controller supports wakeup on the detection ofthe following eventsResumeRemote wakeupSession request protocolNew session startPHY Interface UnitThe USB OTG controller supports synchronous SDR data transmission to a ULPI PHY. The SDR modeimplements an eight bit data busAltera CorporationUSB 2.0 OTG ControllerSend Feedback2015.05.04ULPI PHY Interface 18-9ULPI PHY InterfaceTable 18-1 ULPI PHY InterfacesThe ULPi PHY interface is synchronous to thesignal coming from the phyPort nameWidthDirectionDescriptionInputULPI ClockReceives the 60 MHz clock supplied by thehigh speed uLPi Phy. all signals are synchronousto the positive edge of the clockULPI Data Bus control1-The phy has data to transfer to the usb otgcontroller0-The phy does not have data to transferInputULPI Next data ControlIndicates that the phy has accepted the currentbyte from the usb otg controller. when the phyis transmitting, this signal indicates that a new byteis available for the controllerOutput ULPI Stop Data ControlThe controller drives this signal high to indicate theend of its data stream. The controller can also drivethis signal high to request data from the PhY.8 Bidirectional Bidirectional data bus. Driven low by the controllerduring idleLocal Memory BufferThe NaNd flash controller has three local SRAM memory buffersThe write FIfO buffer is a 128 X 32-bit memory(512 total bytes)The read fifo buffer is a 32 x 32-bit memory(128 total bytes)The eCC buffer is a 96X 16-bit memory(1536 total bytes)The SPRam is a 8192 x 35-bit(32 data bits and 3 control bits)memory and includes support for ECC(Error Checking and Correction). The ECC block is integrated around a memory wrapper. It providesoutputs to notify the system manager when single-bit correctable errors are detected(and corrected)andwhen double-bit uncorrectable errors are detected The ECC logic also allows the injection of single -anddouble-bit errors for test purposes. The ecc feature is disabled by default. It must be initialized to enablethe ecc functionUSB 2.0 OTG ControllerAltera CorporationSend FeedbackCV 5v4Clocks2015.05.04ClocksTable 18-2: USB OTG Controller Clock In putsAll clocks must be operational when reset is released. No special handling is required on the clocksClock SignalFrequencyFunctional Usage60-200 MHz Drives the master and slave interfaces, DMA controller,andinternal fifo buffers60 MHZULPI reference clock for usb0 from external ULPI PHY I/O pin60 MHZULPI reference clock for usbl from external ULPI PHy I/o pinResetsThe USB OtG controller can be reset either through the hardware reset input or through softwareReset requirementsThere must be a minimum of 12 cycles on theclock before the controller is taken out of resetDuring reset, the USB OTG controller asserts thesignal. The PhY outputs a clock when it seesthesignal asserted. However, if the pin multiplexers are not programmed, the Phy does not seethsignal. As a result, theclock signal does not arrive at the USB Otg controllerSoftware must ensure that the reset is aclive for a minimum of lwocycles. There is nomaximum assertion timeHardware resetEach of the USB otG controllers has one reset input from the reset manager The reset signal is assertedduring a cold or warm reset event. The reset manager holds the controllers in reset until software releasesthe resets. Software releases resets by clearing the appropriate USB bits in the Peripheral Module resetRegisterin the hps reset managerThe reset input resets the following blocksThe master and slave interface logicThe integrated DMa controlleThe internal fifo buffersThe CSrThe reset input is synchronized to thedomain. The reset input is also synchronized to theULPI clock within the USB OTG controller and is used to reset the UlPI Phy domain logicSoftware resetSoftware can reset the controller by setting the Core Soft Resetbit in the reset registerin the global registers(group of the USB OTg controlAltera CorporationUSB 2.0 OTG ControllerSend Feedback