xilinx pcie ip doc

pcie ip 后端用户手册&A XILINXChapter 5: Constraining the CoreRequired constraint Modifications.226Device, Package, and speed Grade Selections,,,,,,,.227Core I/0 Assignments............。228Core Physical Constraint228Core Timing Constraints∴∴∴∴229Relocating the Integrated block Core.……………229Supported Core Pinouts230Chapter 6: Getting Started Example DesignDirectory and File Contents233Example design.Generating the coreImplementation..,,,。,,,,,,,,,,,,,,,,,246Simulation,,,247Chapter 7: Example Design and Model Test Bench for Endpoint ConfigurationProgrammed Input/Output: Endpoint Example Design,,,,,,249Root Port Model Test Bench for Endpoint...……∴264Chapter 8: Example Design and Model Test Bench for Root Port ConfigurationConfigurator Example design.........,,.......,,280Endpoint Model test Bench for root port,,,,,,,。,,,286Chapter 9: PIPE Mode SimulationsSECtION I: SE DESIGN SUITEChapter 10: Customizing and generating the coreGUI291Output Generation317Chapter 11: Constraining the CoreRequired Constraint Modifications,,,,,,,,,,,318Device, Package, and Speed grade Selections..............,...... 319Core l/o Assignments..............................320Core physical Constraints320Core Timing Constraints.....321Relocating the Integrated block Core3217SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012&A XILINXSupported Core Pinouts322Chapter 12: Getting Started Example DesignDirectory and File Contents..…,…326Example Design ..332Generating the Core..,...,335Implementation.。338Simulation,,,,,,,,,,,,,,,,,,,,,,,,,,,,339Chapter 13: Example Design and Model Test Bench for Endpoint ConfigurationProgrammed Input/Output: Endpoint Example Design341Root port Model test bench for Endpoint,,356Chapter 14: Example design and Model Test Bench for root port ConfigurationConfigurator Example Design,,,,,,,,,,..372Endpoint model test bench for root port......................378Chapter 15: PIPE Mode SimulationsSECtION V: APPENDICESAppendix A: MigratingMigration Considerations.....n,383TRN to AXI Migration Considerations.....,386Appendix B: DebuggingFindingHelponXilinx.com,,,,,..395Contacting Xilinx Technical Support。396Debug tools....397Hardware Debug.................................400Simulation Debug................................ 411Appendix C: Managing Receive-Buffer Space for Inbound CompletionsGeneral Considerations and Concepts416Methods of Managing Completion Space418Appendix D: PCIE_2_1 Port DescriptionsClock and reset interface423Transaction Layer Interface,424Block ram interface,,,。..4287SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012&A XILINXGTX Transceiver Interface..429Configuration Management Interface........................436Dynamic Reconfiguration Port Interface·.·······.·····:·..·.····..···467Debug Interface Ports.…,,,…,。,。,,467TL2 Interface Ports468Appendix E: Additional resourcesXilinx resources470Solution centers着·音鲁。D曹着鲁·曹·着春。鲁D。·鲁曹看470References,,,,,,,,,.470Technical Support471Revision History472Notice of disclaimer4727SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012&A XILINXSECTION I: SUMMARYIP FactsOverviewProduct specificationDesigning with the Core7SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012&A XILINXIP FactsIntroductionLogiCORE IP Facts TableCore SpecificsThe logiCoRE TM IP 7 Series FPGAs IntegratedBlock for PCi Express core is a scalableSupportedDevicehigh-bandwidth, and reliable serial interconnectZyng-70002),Virtex(R)-7, KinteXTM-7, ArtiXTM-7Family(l)building block for use with Xilinx R Zynq-7000 AllProgrammable SoC(System on a Chip), andSupportedUser interfacesAXI4-Stream7 series FPGa families. The Integrated block forPCI Express(PCIeR) solution supports 1-laneResourcesSee Table 2-22-lane 4-lane and 8-lane endpoint and root portProvided with coreconfigurations at up to 5 Gb/s(Gen2)speeds, allISE: Verilog/VHDL(3)RTL Source and Simulationof which are com pliant with the pc express baseDesign fileModelSpecification, rev. 2.1. This solution supports theVivado: Encrypted rtlAMBAR AXI4-Stream interface for the customerExampleuser interfaceVerilog VHdlDesignWith higher bandwidth per pin, low overhead, lowTest benchVerilog, VHDLlatency, reduced signal integrity issues, and CDRConstraintsarchitecture the integrated block for pcie setsFile∨vado.XDCthe industry standard for a high-performance,SimulationVerilog vHDlcost-efficient, third-generation Iyo solutionModelSupportedThe integrated block for PCi Express solution isN/AS/W Drivecompatible with industry-standard applicationTested Design Flowsorm factors such as the pc/ express cardElectromechanical(CEM)v2.0 and the pclDesign EntryISE R Design Suite v14.3Vivado TM Design Suite v20123(5)Industrial Computer Manufacturers Group(PICMG)3.4 specificationsCadence Incisive Enterprise Simulator(IES)ynapsys vcs and VCS MXSimulationMentor Graphics ModelSimFeaturesXilinx iSimVivada simulatorHigh-performance, highly flexible, scalable,SynthesisXilinx Synthesis Technology(XST)and reliable, general-purpose I/o coreVivado SynthesisCompliant with the PC/ Express BaseSupportSpecification, rev. 2.1ProvidedbyXilinx@www.xilinx.com/supportCompatible with conventional PCIsoftware modelNotes1. For a complete listing of supported devices, see the releaseIncorporates Xilinx Smart-IP technology toguarantee critical timing2. Support for Zyng-7000 devices is not available in Vivado DesignSuite 2012.3Uses GTXE2 or GTPE2 transceivers for 7 series 3. RTL source for the GTX wrapper is Verilog only. VHDL projectsFPGA familiesrequire mixed language mode simulators2.5 GT/s and 5.0 GT/s line speeds4. For the supported versions of the tools see the xilinx designTools: Release Notes guideSupports 1-lane, 2-lane, 4-lane, and5. Supports only 7 series devices8-lane operationElastic buffers and clock compensationAutomatic clock data recovery7SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054 October 16.2012Product specification&A XILINXFeatures(Continued)Supports endpoint and root port configurations8B/10B encode and decodeSupports lane reversal and lane polarity Inversion per PCI Express specification requirementsStandardized user interfaceSupports AXI4-Stream interfaceEasy-to-use packet-based protocolFull-duplex communicationBack-to-back transactions enable greater link bandwidth utilizationSupports flow control of data and discontinuation of an in-process transaction in transmitdirectionSupports flow control of data in receive directionCompliant with PCI/PCI Express power management functionsSupports a maximum transaction payload of up to 1024 bytesSupports Multi-Vector MSI for up to 32 vectors and MSI-XUp-configure capability enables application driven bandwidth scalabilityCompliant with PCI Express transaction ordering rules7SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054 October 16.2012Product specification&A XILINXChapter 1OverⅰeWXilinx( 7 series FPGAs include three unified FPGa families that are all designed for lowestpower to enable a common design to scale across families for optimal power performanceand cost. The artiX TM-7 family is optimized for lowest cost and absolute power for thehighest volume applications. The Virtex-7 family is optimized for highest systemperformance and capacity. The Kintex TM-7 family is an innovative class of fPgas optimizedfor the best price to performance. this document describes the function and operation ofthe 7 Series FPGAs Integrated Block for PCI Express, including how to design, customize,and implement itThe logiCoRETM IP 7 Series FP GAs Integrated Block v1.7 for PCI Express core is a reliable,high-bandwidth, scalable serial interconnect building block the core instantiates the7 Series FPGA Integrated Block for PCI Express found in the 7 series FPGAs, and supportsboth Verilog and VHDL. This Integrated block for PCIe simplifies the design process andreduces time to market. It is configurable for Endpoint and root port applications. Thissolution can be used in communication, multimedia, server and mobile platforms andenables applications such as high-end medical imaging, graphics intensive video games,DVd quality streaming video on the desktop, and 10 Gigabit Ethernet interface cardsAlthough the 7 Series FPGAs Integrated Block for PCI Express core is a fully verifiedsolution, the challenge associated with implementing a complete design varies dependingon the configuration and functionality of the applicationRECOMMENDED: For the best results, previous experience building high-performance pipelined FPGadesigns using Xilinx implementation software and constraints files is recommendedFeature SummaryThe 7 Series FPGAs Integrated block for PCI Express follows the PC/ Express BaseSpecification, rev. 2. 1 [Ref 2] layering model, which consists of the Physical, Data Link andTransaction Layers. The protocol uses packets to exchange information between layersPackets are formed in the transaction and Data Link Layers to carry information from thetransmitting component to the receiving component Necessary information is added tothe packet being transmitted which is required to handle the packet at specific layersThe functions of the protocol layers include7SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012&A XILINXChapter 1: OverviewGenerating and processing of TLpsFlow-control managementInitialization and power management functionsData protectionError checking and retry functionsPhysical link interface initializationMaintenance and status trackingSerialization, deserialization, and other circuitry for interface operationApplicationsThe Xilinx 7 series FPGAs Integrated Block for PCI Express architecture enables a broadrange of computing and communications target applications, emphasizing performance,cost, scalability, feature extensibility and mission-critical reliability. Typical applicationsincludeData communications networksTelecommunications networksBroadband wired and wireless applicationsCross-connectsNetwork interface cardsChip-to-chip and backplane interconnectCrossbar switchesWireless base stationsLicensing and ordering InformationThis Xilinx logicoRE IP module is provided at no additional cost with the Xilinx vivadoTmDesign Suite and ise design suite tools under the terms of the Xilinx End User LicenseInformation about this and other Xilinx logicoRE IP modules is available at the XilinxIntellectual Property page For information about pricing and availability of other XilinxLogiCORE IP modules and tools, contact your local Xilinx sales representativeFor more information, visit the 7 Series FPGAs Integrated Block for PCI Express productpage7SeriesIntegratedBlockforPcle(v1.7)www.xilinx.comPG054。 October16.2012