ARM® Cortex® A57 MPCore Processor Technical Reference Manual.pd

ARM开发必备ARM Cortex -A57 MPCore ProcessorARM Limited Company 02557590 registered in England110 Fulbourn Road. Cambridge England cb1 9NJLES-PRE-20349Confidentiality StatusThis document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions inaccordance with the terms of the agreement entered into by ARM and the party that arm delivered this document toUnrestricted access is an arm internal classificationProduct Statushe inforimation in this docunent is Final, that is for a developed productWeb addresshttp://www.arm.comARM DDIO488GCopyright C 2013, 2014 ARM. All rights reservedContentsARMe Cortex@-A57 MPCore Processor TechnicalReference manualPrefaceabout this bookFeedback12Chapter 1Introduction1. 1 About the Cortex-A57 processor1-141.2 Compliance…1-151.3Features.....1-171.4 terraces…1-181.5Implementation options1-19Test features1-201.7 Product documentation and design flow1-211.8 Product revisions1-23Chapter 2Functional Description2.1 About the Cortex-A57 processor functions2-252.2 nterfaces…………2-292.3 Clocking and resets2-322.4Power management.2-42Chapter 3Programmers Mode3. 1 About the programmers model.3-60ARM DDIO488GCopyright C 2013, 2014 ARM. All rights reserved3. 2 ARMv8-A architecture concepts3-613.3 Humble instruction set3-693.4Jazelle implementation44i3-703.5 Memory model3-72Chapter 4System Control4.1About system control4-744.2 AArch64 register summary..4-754.3AArch64 register descriptions4-884.4 AArch32 register summary4-2114.5AArch32registerdescriptions......4-236Chapter 5Memory Management Unit5.1About the mmu5-2735.27 LB organization.…5-2745.3TLB match process5-2755.4 Memory access sequence5-2765.5 MMU enabling and disabling5-2785.6 ntermediate table walk caches5-2795.7 Externa/aborts5-280Chapter 6Level 1 Memory System6. 1 About the L1 memory system6-2826.2 Cache organization...6-2836.3 L1 instruction memory system6-2846.4 L1 data memory system6-2866.5 Program flow prediction6-2926.6L1 RAM memories6-294Chapter 7Level 2 Memory System7. 1 About the L2 memory system7-2967.2Cache organization7-2977.3L2 RAM memories7-3037.4 L2 cache prefetcher7-3047.5Cache coherency7-3057.6 Asynchronous errors7-3067.7 EXternal coherent interfaces7-3077.8 ACP7-314Chapter 8Generic Interrupt Controller CPU Interface8.1 About the g|C…8-3168.2GIC functional description8-3178.3 G/C programmers model8-322Chapter 9Generic Timer9. 1 About the generic imer9-3369.2Generic Timer functional descriptio9-3379.3 Generic Timer register summary9-338Chapter 10Debug10.1 About debug…10-341ARM DDIO488GCopyright C 2013, 2014 ARM. All rights reserved10.2 Debug register interfaces10-34310.3 AArch64 debug register summary…………10-34510.4 AArch64 debug register descriptions.10-34710.5 AArch 32 debug register summary10-35310.6 AArch32 debug register descriptions10-35510.7 Memory-mapped register summary10-35910.8 Memory-mapped register descriptions10-36310.9 Debug events…10-37710. 10 EXternal debug interface.10-37810.11 ROM table10-381Chapter 11Performance Monitor Unit11.1 About the pmu11-39311.2 PMU functional description11-39411.3 AArch64 PMU register summary11-39611.4 AArch64 PMU register descriptions11-39811.5 AArch32 PMU register summary11-40311.6 Memory-mapped register summary11-40511.7 Memory-mapped register descriptions11-40811.8 Events11-4251.9 Interrupts11.10 EXporting PMU events11-430Chapter 12Cross Trigger12. 1 About the cross trigger12-43212.2 Trigger inputs and outputs12-43312.3C7新444412-4342.4C7M12-43512.5 Cross trigger register summary12-43612.6 Cross trigger register descriptions..12.439Chapter 13Embedded trace macrocell13.1 About eTm..13-45513.2 ETM trace generation options and resources13-45613.3 ETM functional description∴13-45813.4 Reset13-45913.5 ETM register interfaces13-46013.6 Register summary13-46113.7 Register descriptions13-46513.8 Interaction with debug and the Performance Monitor Unit13-507Chapter 14Advanced SIMD and Floating-point14.1 About Advanced SIMD and Floating-point14-50914.2 Programmers mode/ for Advanced S/MD and Floating-point .......................14-51014.3 AArch64 register summary14-51114.4 AArch64 register de14-51214.5AArch32 register summary14-52114.6 AArch 32 register descriptions14-522AppendⅸxASignal DescriptionsA 1 About the signal descriptionsAppx-A-527ARM DDIO488GCopyright C 2013, 2014 ARM. All rights reservedA 2 Clock signalsAppx-A-528A.3尺 eset signa/s………Appx-A-529A 4 Contiguration signals.. Appx-A-530A.5GIC CPU interface signalsAppx-A-532A6 Generic /imer signalsAppx-A-534A 7 Power control signals.......... Appx-A-535A8 ACE and CH/ interface signalsAppx-A-537A9 CH/ interface signals..ppX-A-540A 10 ACE interface signalsAppx-A-545A 11 ACP interface signalsAppx-A-550A 12 Debug interface signals….Appx-A-553A13 EM interface….Appx-A-556A 14 Cross trigger channel interfaceAppx-A-558A 15 PMU signalsAppx-A-559A 16 DF/ and MB/S/ signals4ppx-A-560Appendix BAArch32 Unpredictable BehaviorsB.1 Unpredictable behaviors………Appx-B-562B.2Debug UNPREDICTABLE behaviorsAppX-B-564Appendix CRevisionsC.1RevisionsAppx-C-572ARM DDIO488GCopyright C 2013, 2014 ARM. All rights reservedPrefaceThis preface introduces the ARM Cortex -A57 MPCore Processor Technical reference manualIt contains the followingAbout this book on page 9.Feedback on page 12ARM DDIO488GCopyright C 2013, 2014 ARM. All rights reserved8Prefaceabout this bookAbout this bookThis document describes the aRM Cortex -A57 processorProduct revision statusThe rmpn identifier indicates the revision status of the product described in this book, for example, r1p2rm Identifies the major revision of the product, for example, rlpn Identifies the minor revision or modification status of the product, for example, p2Intended audienceThis document is written for system designers, system integrators, and programmers who are designingor programming a System-on-Chip (soc) that uses the Cortex-A57 processorUsing this bookThis book is organized into the following chaptersChapter 1 IntroductionThis chapter introduces the Cortex -A57 processor and its featuresChapter 2 Functional DescriptionThis chapter describes the functionality of the Cortex- A57 processorChapter 3 Programmers ModelThis chapter describes the processor registers and provides information for programming theprocessorChapter 4 System ControlThis chapter describes the System registers, their structure, operation, and how to use themChapter 5 Memory Management UnitThis section describes the Memory Management Unit (MMU)Chapter 6 Level 1 Memory SystemThis section describes the Level /(Ll) memory systemChapter 7 Level 2 Memory SystemThis chapter describes the Level 2(L2)memory systemChapter 8 Generic Interrupt Controller CPU InterfaceThis section describes the Cortex-A57 processor implementation of the GIC CPU interfaceChapter 9 Generic TimerThis chapter describes the Cortex-A57 processor implementation of the ARM Generic TimerChapter 10 DebugThis section describes the Cortex-A57 processor debug registers and shows examples of how toChapter 11 Performance Monitor UnitThis section describes the Performance Monitor Unit(PMU) and the registers that it usesChapter 12 Cross TriggerThis chapter describes the cross trigger interfaces for the Cortex -A57 processorChapter 13 Embedded Trace MacrocellThis section describes the Embedded Trace Macrocell (EtM) for the Cortex-A57 processorChapter 14 Advanced SIMD and Floating-pointThis chapter describes the Advanced SIMD and Floating-point features and registers in theCortex-A57 processorARM DDIO488GCopyright C 2013, 2014 ARM. All rights reservedPrefaceAbout this bookAppendix A Signal DescriptionsThis section describes the Cortex-A57 processor signalsAppendix B AArch 32 Unpredictable BehaviorsThis appendix describes specific Cortex-A57 processor UNPREDICTABLE behaviors that are ofrticular interestAppendix C RevisionsThis appendix describes the technical changes between released issues of this bookGlossaryThe ARM Glossary is a list of terms used in arm documentation together with definitions for thoselerms. The ARM Glossary does not contain terns that are industry standard unless the ARM meaningdiffers from the generally accepted meaningSee the ARM Glossary for more informationTypographic conventionsIntroduces special terminology, denotes cross-references, and citationsHighlights interface elements, such as menu names. Denotes signal names. Also used for termsin descriptive lists, where appropriatemonospaceDenotes text that you can enter at the keyboard, such as commands, file and program namesand source codemonos paceDenotes a permitted abbreviation for a command or option. You can enter the underlined textinstead of the full command or option namemonospace italicDenotes arguments to monospace text where the argument is to be replaced by a specific valuemonospace boldDenotes language keywords when used outside example codeEncloses replaceable terms for assembler syntax where they appear in code or code fragmentsFor example:MRC p15,0,, ,, SMALL CAPITALSUsed in body text for a few terms that have specific technical meanings, that are defined in theARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, andUNPREDICTABLETiming diagramsThe following figure explains the components used in timing diagrams. Variations, when they occur,have clear labels. You must not assume any timing information that is not explicit in the diagramsShaded bus and signal areas are undefined so the bus or signal can assume any value within the shadedarea at that time. The actual level is unimportant and does not affect normal operationARM DDIO488GCopyright C 2013, 2014 ARM. All rights reserved