1.Found clock-sensitive change during active clock edge at time on register ""原因:vector source file 中时钟敏感信号(如:数据,允许端,清零,同步加 载等) 在时钟的边缘同时变化.而时钟敏感信号是不能在时钟边沿变化的.其后 果为导 致结果不正确.措施:编辑 vector source file2.Verilog HDL assignment warning at : truncated with size to match size
