hello 自动循环 EDA

EDA工程 hello FPGA library ieee; use ieee.std_logic_1164.all; entity ex7_part2_top is port (sw :in std_logic_vector(17 downto 0); hex0: out std_logic_vector(6 downto 0); hex1: out std_logic_vector(6 downto 0); hex2: out std_logic_vector(6 downto 0); hex3: out std_logic_vector(6 downto 0); h