Timing And Patterns

By Dirk Hill ================ Timing and Patterns • Timing Diagram • Timing • Formats • Timing II • Patterns • Bringing It All Together This is a short paper on the basics of test development. This one covers developing a set of formats, timing sets and a pattern from a timing diagram and timing table. The device used is a simple SRAM memory device with a multiplexed bus. It has 16 memory locations accessed by four parallel address/data lines. There are three control lines: Address Latch Enable (ALE), Write enable (WR), and Read enable (RD). To access a memory location the address must first be latched and then either a read or write cycle follows. (Once an address is latched multiple Writes and Reads can take place on the same location. We do not take advantage of this in this paper.) This paper does not take DC parametrics into consideration. The “tester” is a simplified one with a tester-per-pin architecture (that is all the pins are input and output pins). It is capable of timeset and format switching on the fly. It has 4 edgesets and 4 format sets per pin and 10 time sets. (We do not take advantage of format switching on the fly in this paper.) enable (RD). To access a memory location the address must first be latched and then either a read or write cycle follows. (Once an address is latched multiple Writes and Reads can take place on the same location. We do not take advantage of this in this paper.) This paper does not take DC parametrics into consideration. The “tester” is a simplified one with a tester-per-pin architecture (that is all the pins are input and output pins). It is capable of timeset and format switching on the fly. It has 4 edgesets and 4 format sets per pin and 10 time sets. (We do not take advantage of format switching on the fly in this paper.)