EDA 12864 verilog 程序

modulenewlcd(clk,rst,lcd_e,lcd_rs,lcd_rw,data,lcd_psb); inputclk; inputrst; //inputlcd_ret; outputlcd_psb; outputlcd_e; outputlcd_rs; outputlcd_rw; output[7:0]data; reglcd_e; reglcd_rw; reglcd_rs; reg[7:0]data; reg[21:0]clkcnt; regclkdiv; regdouble_div; regflag; reg[7:0]state;