STM32F2xx用户手册

RM0033 Contents Powercontrol(PWR) 62 4.1Powersupplies .62 4.1.1Independenta/convertersupplyandreferencevoltage 4.1.2Batterybackupdomain 63 4.1.3Voltageregulator 65 4.2Powersupplysupervisor.....................................66 2 Power-onreset(POR)/power-downreset(PDR) 66 4.2.2Brownoutreset(BOR) 67 4.2.3Programmablevoltagedetector(PVD) 4.3LOW-powermodes 68 4.3.1Slowingdownsystemclocks ..69 4.3.2Peripheralclockgating 69 4.3.3Sleepmode 70 4.3.4Stopmode 4.3.5Standbymode 72 4.3.6ProgrammingthertCalternatefunctionstowakeupthedevicefrom theStopandStandbymodes 74 4.4Powercontrolregisters 4.4.1PWRpowercontrolregister(PWRCR) 4.4.2PWRpowercontrol/statusregister(PWR_CSR) ..,78 4.4.3PWRregist 79 Resetandclockcontrol(Rcc) 80 5.1Reset 80 5.1.1Systemreset 翻1面 80 5.1.2Powerreset 81 5.1.3Backupdomainreset 82 5.2Clocks 82 5.2.1HSEclock 84 522 HSIclock .85 5.2.3PLLconfiguration .86 5.2.4LSEclock 86 5.2. LSIclock 5.2.6Systemclock(SYSCLK)selection 87 5.2.7Clocksecuritysystem(Css 87 5.2.8RTC/AWUclock 88 5.2.9Watchdogclock 88 DocID15403Rev2 3/1307 Contents RM0033 5.2.10Clock-outcapability 89 5.2.11Internal/externalclockmeasurementusingtiM5/TIM11 89 5.3RCCregisters 9 5.3.1RCCclockcontrolregister(RCC_CR) 5.3.2RCCPLLconfigurationregister(RCC_PLLCFGR) 93 5.3.3RCCclockconfigurationregister(RCC_CFGR) 95 5.3.4RCCclockinterruptregister(RCC_CIR) 5.3.5RCCAHB1peripheralresetregister(RCC_AHB1RSTR) 100 5.3.6RCCAHB2peripheralresetregister(RCC_AHB2RSTR) ....102 5.3.7RCCAHB3peripheralresetregister(RCC_AHB3RSTR) ,,.,103 5.3.8RCCAPB1peripheralresetregister(RCCAPB1RSTR) 103 5.3.9RCCAPB2peripheralresetregister(RCC-APB2RSTR) .106 5.3.10RCCAHB1peripheralclockregister(RCC_AHB1ENR) 108 5.3.11RCCAHB2peripheralclockenableregister(RCC_AHB2ENR) 110 5.3.12RCCAHB3peripheralclockenableregister(RCC_AHB3ENR) 11 5.3.13RCCAPB1peripheralclockenableregister(RCC_APB1ENR) .111 5.3.14RCCAPB2peripheralclockenableregister(RCC_APB2ENR) 114 5.3.15RCCAHB1peripheralclockenableinlowpowermoderegister (RCC_AHB1LPENR) 116 5.3.16RCCAHB2peripheralclockenableinlowpowermoderegister 5.3.17RCCAHB3peripheralclockenableinlowpowermoderegister..118 (RCC_AHB2LPENR) (RCC_AHB3LPENR 119 5.3.18RCCAPB1peripheralclockenableinlowpowermoderegister (RCC_APB1LPENR) ,,,,,,.120 5.3.19RCCAPB2peripheralclockenabledinlowpowermoderegister (RCC_APB2LPENR) 123 5.3.20RCCBackupdomaincontrolregister(RCC_BDCR) ,,,,,125 5.3.21Rccclockcontrolstatusregister(RCCCSR .126 5.3.22RCCspreadspectrumclockgenerationregister(RCC_SSCGr)..128 5.3.23RCCPLLI2Sconfigurationregister(RCC_PLLI2SCFGR).....129 5.3.24RCCregistermap 13 General-purposeOs(GPIO) 134 6.1GPOintroduction ,,.134 6.2GPIOmainfeatures 134 6.3GPIOfunctionaldescription ,,,,,134 6.3.1General-purposeIO(GPlO) 4/1307 DocID15403Rev2 RM0033 Contents 6.3.20pinmultiplexerandmapping .137 6.3.310portcontrolregisters 139 6.3.410portdataregisters 139 6.3.5odatabitwisehandling .140 6.3.6GPIOlockingmechanism 翻 .140 6.3.7l/0alternatefunctioninput/output 翻D 140 6.3.8EXternalinterrupt/wakeuplines ,141 6.3.9Inputconfiguration 141 6.3.10Outputconfiguration 142 6.3.11Alternatefunctionconfiguration 142 6.3.12Analogconfiguration ,,143 6.3.13UsingtheOSC32_IN/OSC32_OUTpinsasGPIOPC14/PC15 portpins 144 6.3.14UsingtheOSC_IN/OSC_OUTpinsasGPIOPHO/PH1portpins..144 6.3.15Selectionofrtcaflandrtcaf2alternatefunctions ,144 6.4GPIOregisters 146 6.4.1GPIoportmoderegister(GPlOX_MODER)(X=A.I) .146 6.4.2GPIOportoutputtyperegister(GPIOX_OTYPER)(X=A.1).......146 6.4.3GPlOportoutputspeedregister(GPIOX_OSPEEDR) (x=A. 147 6.4.4GPIOportpull-up/pull-downregister(GPIOX_PUPDR) (X=A.) 147 6.4.5GPIOportinputdataregister(GPIOX_IDR(X=A.I ,,148 6.4.6GPIOportoutputdataregister(GPIOX_ODR)(x=A.I).....148 6.4.7GPlOportbitset/resetregister(GPIOX_BSRR)(x=A.D) 148 6.4.8GPloportconfigurationlockregister(GPIOx_LCKR) X=A.I) 149 6.4.9GPlOalternatefunctionlowregister(GPlO_AFRL)(x=A.)...150 6.4.10GPIoalternatefunctionhighregister(GPIOX_AFRH) (x=A.) 15 6.4.11GPlOregistermap ...151 7 Systemconfigurationcontroller(SYSCFG) 153 7.11/0compensationcell 153 7.2SYSCFGregisters 153 7.2.1SYSCFGmemoryremapregister(SYSCFG_MEMRMP).....153 7.2.2SYSCFGperipheralmodeconfigurationregister(SYSCFG_PMC).155 7.2.3SYSCFGexternalinterruptconfigurationregister1 (SYSCFG_EXTICR1 ......155 DocID15403Rev2 5/1307 Contents RM0033 7.2.4SYSCFGexternalinterruptconfigurationregister2 (SYSCFG_EXTICR2 156 7.2.5SYSCFGexternalinterruptconfigurationregister3 (SYSCFG_EXTICR3 156 7.2.6SYSCFGexternalinterruptconfigurationregister4 (SYSCFG_EXTICR4 .157 7.2.7Compensationcellcontrolregister(SYSCFG_CMPCR) 157 7.2.8SYSCFGregistermaps 158 Interruptsandevents..::..,,.. 159 8.1Nestedvectoredinterruptcontroller(NVIC)............159 8.1.1NVICfeatures 159 8.1.2SysTickcalibrationvalueregi 159 8.1.3Interruptandexceptionvectors 159 8.2Externalinterrupt/eventcontroller(EXTI) 163 8.2.1EXTImainfeatures 163 8.2.2EXTIblockdiagram .......163 8.2.3Wakeupeventmanagement .164 8.2.4Functionaldescription 164 8.2.5EXternalinterrupt/eventlinemapping 165 8.3EXTIregisters 166 8.3.1Interruptmaskregister(EXTI_IMR) 166 8.3.2Eventmaskregister(EXTI_EMR) .166 8.3.3Risingtriggerselectionregister(EXTI_RTSR) ,,,,,,167 8.3.4Fallingtriggerselectionregister(EXTI_FTSR .167 8.3.5Softwareinterrupteventregister(EXTI_SWIER 168 8.3.6Pendingregister(EXTI_PR) 168 8.3.7EXTIregistermap 169 DMAcontroller(DMA) ,,,,,.170 9.1dMaintroduction 170 9.2DMAmainfeatures 171 9.3DMAfunctionaldescription 172 9.3.1 G 172 9.3.2DMAtransactions ,,,.,,173 9.3.3Channelselectio 174 9.3.4Arbiter 175 DocID15403Rev2 RM0033 Contents 9.3.5DMAstreams .175 9.3.6Sourcedestinationandtransfermodes ..176 9.3.7Pointerincrementation 179 9.3.8Circularmode 180 9.3.9Doublebuffermode 180 9.3.10Programmabledatawidth,packing/unpacking,endianess.....181 9.3.11Singleandbursttransfers ..183 9.3.12FFO 183 9.3.13DMAtranstercompletion 186 9.3.14DMAtransfersuspension 187 9.3.15Flowcontroller 187 9.3.16SummaryofthepossibleDMAconfigurations .188 9.3.17Streamconfigurationprocedure .189 9.3.18Errormanagement 190 9.4DMAinterrupts 19 9.5DMAregisters 191 9.5.1DMAlowinterruptstatusregister(DMA_LISR) 9.5.2DMahighinterruptstatusregister(DMA_HISR) .192 9.5.3DMAlowinterruptflagclearregister(DMA_LIFCR) 193 9.5.4DMAhighinterruptflagclearregister(DMA_HIFCR) 194 9.5.5DMAstreamxconfigurationregister(DMA_SXCR)(X=0.7) 195 9.5.6DMAstreamxnumberofdataregister(DMA_SXNDTR)(X=0.7).198 9.5.7DMAstreamxperipheraladdressregister(DMA_SxPAR)(x=0.7).198 9.5.8DMAstreamxmemoryoaddressregister(DMA_SXMOAR)(x=0.7)199 9.5.9DMAstreamxmemory1addressregister(DMA_SXM1AR)(x=0.7)199 9.5.10DMAstreamxFIFOcontrolregister(DMA_SxFCR)(x=0.7) 200 9.5.11DMAregistermap ....201 10 Analog-to-digitalconverter(ADc) 205 10.1ADCintroduction 205 10.2ADCmainfeatures 205 10.3ADCfunctionaldescription 205 10.3.1ADcon-offcontrol 207 10.3.2ADCclock 207 10.3.3Channelselection ,,207 10.3.4Single 208 10.3.5Continuousconversionmode 208 DocID15403Rev2 7/1307 Contents RM0033 10.3.6Timingdiagram .209 10.3.7Analogwatchdog 209 10.3.8Scanmode 10.3.9Injectedchannelmanagement 210 10.3.10Discontinuousmode 21 10.4Dataalignment 212 10.5Channel-wiseprogrammablesamplingtime ,,,,,213 10.6Conversiononexternaltriggerandtriggerpolarity 214 10.7Fastconversionmode 215 10.8Datamanagement 216 10.8.1UsingtheDMA ..216 10.8.2ManagingasequenceofconversionswithoutusingtheDMA 216 10.8.3Conversionswithoutdmaandwithoutoverrundetection .216 10.9MultiADCmode ■ ,,,,,217 10.9.1Injectedsimultaneousmode ...,,220 10.9.2Regularsimultaneousmode 221 10.9.3Interleavedmode 222 10.9.4Alternatetriggermode ..224 10.9.5Combinedregular/injectedsimultaneousmode .226 10.9.6Combinedregularsimultaneous+alternatetriggermode 226 10.10Temperaturesensor 227 10.11Batterychargemonitoring 228 10.12ADCinterrupts 229 10.13ADCregisters 230 10.13.1ADCstatusregister(ADC_SR) 230 10.13.2ADCcontrolregister1(ADC_CR1) 23 10.13.3ADCcontrolregister2(ADC_CR2) ......233 10.13.4ADCsampletimeregister1(ADCSMPR1) 10.13.5ADCsampletimeregister2(ADCSMPR2) ...236 10.13.6ADCinjectedchanneldataoffsetregisterX(ADC_JOFRx)(x=1.4).237 10.13.7ADCwatchdoghigherthresholdregister(ADC_HTR) 237 10.13.8ADCwatchdoglowerthresholdregister(ADC_LTR) 237 10.13.9ADCregularsequenceregister1(ADCSQR1) 238 10.1310ADCregularsequenceregister2(ADG_SQR2) 238 10.1311ADCregularsequenceregister3(ADC_SQR3) 239 10.13.12ADCinjectedsequenceregister(ADCJSQR) 239 8/1307 DocID15403Rev2 RM0033 Contents 10.13.13ADCinjecteddataregisterX(ADC_JDRx)(x=1.4) 240 10.13.14ADCregulardataregister(ADC_DR) ..240 10.13.15ADCCommonstatusregister(ADC_CSr) 242 10.13.16ADCcommoncontrolregister(ADC_CCR) 10.13.17ADCcommonregulardataregisterfordualandtriplemodes (ADC_CDR) .245 10.13.18ADCregistermap Digital-to-analogconverter(DAC).......... ■■■■ 248 11.1DACintroduction 248 11.2DACmainfeatures .....248 11.3DACfunctionaldescription 250 11.3.1DACchannelenable ....250 11.3.2DACoutputbufferenable 250 11.3.3DACdataformat .250 113.4DAcconversion 251 11.3.5DACoutputvoltage 252 11.3.6DACtriggerselection 252 11.3.7DMArequest .,.252 11.3.8Noisegeneration ...253 11.3.9Triangle-wavegeneration 254 11.4Dualdacchannelconversion 255 11.4.1Independenttriggerwithoutwavegeneration .255 11.4.2IndependenttriggerwithsingleLFSRgeneration 256 11.4.3IndependenttriggerwithdifferentLFSRgeneration 256 11.4.4Independenttriggerwithsingletrianglegeneration .256 11.4.5Independenttriggerwithditterenttrianglegeneration ....257 11.4.6Simultaneoussoftwarestart 257 11.4.7Simultaneoustriggerwithoutwavegeneration 257 11.4.8SimultaneoustriggerwithsingleLfSRgeneration 258 11.4.9SimultaneoustriggerwithdifferentLFSRgeneration .258 11.4.10Simultaneoustriggerwithsingletrianglegeneration ...,,258 11.4.11Simultaneoustriggerwithdifferenttrianglegeneration .....259 1.5DACregisters 259 11.5.1DACcontrolregister(DAC_Cr 259 11.5.2DACsoftwaretriggerregister(DAC_SWTRIGR) 262 DocID15403Rev2 Contents RM0033 11.5.3DACchannel112-bitright-aligneddataholdingregister DAC_DHR12R1) .263 11.5.4DACchannel112-bitleftaligneddataholdingregister (DAC_DHR12L1) .263 11.5.5DACchannell8-bitrightaligneddataholdingregister DAC_DHR8R1) 263 11.5.6DACchannel212-bitrightaligneddataholdingregister (DAC_DHR12R2 .264 11.5.7DACchannel212-bitleftaligneddataholdingregister (DAC_DHR12L2 264 11.5.8DACchannel28-bitright-aligneddataholdingregister (DAC_DHR8R2) ,,264 11.5.9DualDAC12-bitright-aligneddataholdingregister (DAC_DHR12RD 265 11.5.10DUALDAC12-bitleftaligneddataholdingregister (DAC_DHR12LD) .265 11.5.11DUALDAC8-bitrightaligneddataholdingregister DAC_DHR8RD) 266 11.5.12DACchannelldataoutputregister(DAC_DOR1) 266 11.5.13DACchannel2dataoutputregister(DAC_DOR2 266 11.5.14DACstatusregister(DAC_SR) 11.5.15DACregistermap ,,268 12 Digitalcamerainterface(DCMI) 269 12.1DCMIintroduction 269 12.2DCMImainfeatures 269 12.3DCMIpins 269 12.4DCMIclocks 269 12.5DCMIfunctionaloverview .270 12.5.1DMAinterface 271 12.5.2DCMIphysicalinterface 271 12.5.3Synchronization ..273 12.5.4Capturemodes .275 12.5.5Cropfeature 276 12.5.6JPEGformat 277 12.5.7F|FO 277 12.6Dataformatdescription 278 12.6.1Dataformats ...278 12.6.2Monochromeformat 278 10/1307 DocID15403Rev2