IC Compiler User Guide

Contents WhatsNewinThisrelease Aboutthisguide XXVIll CustomerSupport 1■口 PartI:ICCompilerImplementationFlow IntroductiontoICCompiler Supportedplatforms 1-2 ICCompilerPackages 1-2 UserInterfaces -5 MethodologyOverview ■■■1 1-5 SpeedingUptheBasicFlow 1-8 2.WorkingWithICCompiler GettingStarted 22 StartingICCompiler 22 Enteringicc_shellCommands 2-4 ChoosingmenuCommandsinguiwindows InterruptingorTerminatingcommandprocessing OpeningandClosingthegUI 2-7 UsingTclScripts 28 UsingSetupFiles 2-9 ExitingICCompiler ■■■■■着日■1 2-10 ICCompilerImplementationUserGuide Versiond-201003 GettingHelpinICCompiler 2-11 GettingHelpontheCommandLine 2-11 FindingMenuCommandsandDialogBoxes 212 ViewingManPages 2-14 DisplayingtheListofKeyboardShortcuts 2-14 UsingOnlineHelp 2-15 SearchingforText 2-16 ConfiguringtheHelpBrowser 2-17 WorkingWiththeguI 2-18 UsingGUIWindows 2-18 Menubar 重1 2-19 Toolbars 2-20 Statusbar 2-20 ViewWindows 2-21 Panels 1重 2-22 WorkingintheMainWindow ■■面 2-23 WorkingWiththeConsole 2-24 ViewingtheSessionLog 2-25 ViewingtheHistoryView 2-27 Previewingicc_shellCommandsinDialogBoxes 2-28 ViewingthePhysicalLayout 2-29 SettingthecurrentTask 2-30 SettingthePrimaryDesign 2-31 SettingGUIPreferences 2-31 ReadingandSavingDesigns 2-32 ReadingaDesign 2-33 SettingtheCurrentDesigr 2-34 Savingdesigns 2-34 SavingdesignSettings 2-35 Closingdesigns 2-36 SavingorDiscardingDesignChanges 2-37 Archivingdesigns ■■■■■着日■1 2-39 UsingICCompilerCommand-LineInterfaces 2-41 UsingWildcardCharacters ■ 2-43 UsingAliases 2-43 istingandRerunningPreviouslyEnteredCommands 2-44 ReportingMemoryUsageandRuntime 2-44 Contents ICCompilerImplementationUserGuide Versiond-201003 RedirectingandAppendingcommandoutput 2-44 CheckingtheSyntaxandSemanticsofYourScripts 2-45 InstallationRequiremen 2-46 RunningtheSynopsysSyntaxChecker 2-46 LimitationsoftheSynopsysSyntaxChecker 2-48 Bytecode-CompiledFiles 2-49 TclProLimitations 2-49 WorkingWithLicenses 2-49 ListingtheLicensesinUse 2-50 GettingLicenses 2-50 EnablingLicenseQueuing 2-51 Releasinglicenses 2-52 GettingandReleasingLicensesintheGUI 2-52 EnablingMulticoreProcessing 2-53 ConfiguringMultithreading 2-53 ConfiguringDistributedProcessing 2-54 3.Preparingthedesign SettingUptheLibraries 3-2 SettingUptheLogicLibraries 32 SettingUpthePhysicalLibraries 3-3 CreatingaMilkywayDesignLibrary 3-4 ManagingMilkywayReferenceLibrariesUsing Referencecontrolfiles 3-5 UpdatingMilkywayLibrariestotheLatestSchema 3-10 OpeningaMilkywayDesignLibrary 3-12 ReportingonaMilkywayDesignLibrary 3-12 ChangingPhysicalLibraryInformation 3-13 SavingPhysicalLibraryInformation 3-14 VerifyingLibraryConsistency 3-15 ReadingtheDesign 3-15 ReadingaDesigninMilkywayFormat 3-16 ReadingaDesigninASCllFormat 3-17 AnnotatingthePhysicalData 3-18 ReadingDEFFiles 3-18 ReadingFloorplanFiles 3-19 Contents ICCompilerImplementationUserGuide Versiond-201003 CopyingPhysicalData 3-19 ValidatingPhysicalData 3-21 CheckingtheDesignDatabase 3-21 UsingtheGUIPartitionEditor ■■■■■ 3-22 PreparingforTimingAnalysisandRCCalculation 3-27 SettingUpthetlUPlusFiles 3-27 Back-AnnotatingDelayorParasiticData 重1 3-29 SettingtimingConstraints 3-29 SpecifyingtheOperatingConditionAnalysisMode 3-30 SettingVoltageandTemperatureScalingBetweenLibraries 3-31 SettingtheDeratingFactors 3-32 SelectingtheDelaycalculationMethod 3-33 Savingthedesign 3-34 SavingthedesigninmilkywayFormat 3-34 SavingthedesigninASCllFormat 3-34 WritingGDSIIandOASISLayoutDataFiles 3-35 4.DesignforTest Overviewofthedftflow 4-2 PreparingforPhysicalDFTUsingtheread_defFlow 4-3 PerformingScanSynthesisandGeneratingaSCANDEFFile 4-4 Hierarchicalflov LoadingtheSCANDEFFile 4-5 GeneratingSCANDEFDataUsingthetrace_scan_chainFlow 4-6 ScanChainConsistencyChecking 4-7 RemovingSCANDEFData 4-8 OptimizingScanChains 4-8 Placement-AwareScanChainReordering 4-9 Clock-AwareScanReordering 4-11 ExampleoptimizationFlow iewingScanChains 4-12 Contents ICCompilerImplementationUserGuide Versiond-201003 5.PowerOptimization TypesofPowerOptimization 52 StrategiesToReduceLeakagePower 5-2 UsingMultipleThreshold-VoltageCells 5-3 MultipleThreshold-VoltageLibraries 5-4 DefiningMultipleThreshold-VoltageCellsUsingAttributes ConstrainingtheLeakagePowerOptimization :: 5-5 AdaptiveLeakagePowerOptimization 5-7 AnnotatingSwitchingActivity .· SettingtheOptionsforPowerOptimization 5-8 Performingpoweroptimization 5-9 LoW-PowerPlacement 5-9 LOW-PowerClockTreeSynthesis 5-10 LOW-PowerRouting 1■■■■ 5-10 PowerOptimizationFlowExample 5-11 6.Placement DefiningPlacementBlockages 6-2 DefiningKeepoutMargins 重■重 6-2 DefiningGlobalKeepoutMargi 6-3 DefiningCell-SpecificKeepoutMargins 6-4 DefiningArea-BasedPlacementBlockages 6-5 lacementOpti CongestionOptions 6-7 Movebounds 68 IntercellandBoundarySpacingRules 6-9 ButterStrategyforOptimization 6-11 SettingthePreferredBuffersforHoldFⅸXing...…, 6-11 TieCellInsertion 6-12 MagnetPlacement. 1■ 1■ 6-12 PlacementandOptimizationAttributes 6-14 InsertingPortProtectionDiodes 6-15 PreparingforHigh-FanoutNetsynthesis 6-15 AnalyzingPlacementandOptimizationFeasibility 6-16 Contents ICCompilerImplementationUserGuide Versiond-201003 AnalyzingCellDisplacementDuringLegalization 6-17 PerformingClockTreeSynthesisDuringPlacement 6-19 Performingplacementandoptimization 6-20 UsingPhysicalGuidanceFromDesignCompiler 6-22 SavingIntermediateResultsDuringRerouteOptimization 6-22 SettingUpforCongestion-DrivenPlacement 6-23 UsingPhysicalOptimization 6-24 RerouteRCEstimation ■m 6-26 ModifyingtheRCCoefficients 6-27 DefiningNet-BasedLayerConstraints 6-27 IntroducingPessimism 6-28 EnablingviaResistanceEstimation 6-29 ScalingtheviaResistancevalues 6-29 ManuallySpecifyingViaResistanceValues 6-29 AnalyzingPlacement 6-30 PlacementAreautilization 6-30 TimingAnalysis 6-32 PowerAnalysis 6-37 Quality-of-ResultsReporting 6-39 creategorsnapshot 1■■ 6-40 query_gor_snapshot 6-41 PlacementAnalysisToolsinthegUI 6-43 CellDensityMe 6-44 CongestionMaps 6-46 HierarchyVisualMode 6-47 ClockTreeVisualmode 6-48 NetConnectionsinAreavisualmode ::·: 6-48 RefiningPlacement 6-52 7.ClockTreeSynthesis PrerequisitesforClockTreeSynthesis DesignPrerequIsites… 7-3 LibraryPrerequisites............ AnalyzingtheClockTrees 1■ 7-4 DefiningtheClockTrees 7-5 Contents ICCompilerImplementationUserGuide Versiond-201003 Cascadedclocks 7-6 CascadedGeneratedClocks 1■■■■■ 7-6 IdentifyingtheClockTreeEndpoint 7-7 DefiningtheclockRootAttributes 7-9 SpecifyingclockTreeEXceptions SpecifyingNonstopPins 7-13 SpecifyingEXcludePins 7-13 SpecifyingFloatPin 7-14 SpecifyingStopPins 7-17 SpecifyingDon'tTouchSubtrees 7-17 SpecifyingDon'tBufferNets pecifyingDontsizecells 7-18 SpecifyingSize-OnlyCells 7-19 PreservingtheClockPinsofExistingHierarchies 7-19 SpecifyingtheClockTreeReferences 7-20 DefiningClockCellSpacingRules ■■■ 7-22 SpecifyingClockTreeSynthesisOptions 7-23 SpecifyingtheClockTreeSynthesisGoals 7-27 SettingClockTreeDesignRuleConstraints 7-27 SettingClockTreeTimingGoals 7-29 SettingLevelRestrictions 7-30 SettingClockTreeRoutingOptions 7-30 SpecifyingRoutingRules ■■■ 7-31 ShieldingClockNets 7-32 SpecifyingroutingLayers 7-34 AssociationofNondefaultroutingruleswithreferencecells 7-35 InsertingBoundaryCells 7-36 SelectingtheClockTreeClustering 7-37 EnablingOn-Chip-Variation-AwareClustering 7-38 EnablingLogic-LevelBalancing 7-38 EnablingRegion-AwareClockTreeSynthesis 7-41 SpecifyingClockTreeOptimizationOptions 7-42 ControllingEmbeddedClockTreeOptimization 7-42 ControllingRerouteClockTreeOptimization 7-43 ControllingPostrouteClockTreeOptimization 7-44 SavingIntermediateResultsDuringPrerouteOptimization 44 Contents ICCompilerImplementationUserGuide Versiond-201003 InsertingUser-SpecifiedClockTrees 7-45 ReadingaClockConfigurationFile 7-45 ReducingSkewVariationbyUsingRCConstraint-BasedClustering 7-45 Savingaclockconfigurationfile 7-46 Definingtheclocktreestructure 7-46 HandlingSpecificDesignCharacteristics 7-50 HandlingHardMacroCells ■m■ 7-50 andlingExistingClockTrees 7-51 IdentifyingExistingClockTrees 7-51 PreservingPortionsofanEXistingClockTree 7-52 RemovingClockTrees 7-52 HandlingNon-UnateGatedClocks 7-54 HandlingIntegratedClock-GatingCells 7-54 OptimizingforClockTreeQoR 7-54 OptimizingforPower 7-56 otimizingforTimingonEnableSignals 7-58 BalancingMultipleClocks 7-60 DefiningtheDelayBalancingBuffers 7-60 DefiningaClockBalanceGroup ■1 7-60 DefiningtheInterclockDelayRequirements 7-61 RemovingtheInterlockdelaysettings 7-63 HierarchicalDesignsUsingInterfaceLogicModels 7-64 Multivoltagedesigns 7-64 Multicorner-Multimodedesigns 7-65 /erifyingtheClockTrees 7-65 ImplementingtheClockTrees 7-67 AnalyzingOptimizationFeasibilityAfterClockTreeSynthesis 7-72 StandaloneClockTreeSynthesisCapabilities 7-73 PerformingClockTreePowerOptimization 7-74 PerformingClockTreeSynthesis 7-74 PerformingClockvτerOPimization….… High-FanoutNetSynthesis 7-75 7-76 ImplementingclockMeshes 7-80 PrerequisitesforcreatingclockMeshes 7-81 Theclockmeshflow 7-82 FlatteningtheLogicofIntegratedClock-GatingCells 重1重 7-83 SplittingClockNets 7-84 Contents