DDR4最新规范

PLEASEL DONTVIOLATE THE LAW ThisdocumentiscopyrightedbyJEDECandmaynotbe reproducedwithoutpermission orinformationcontact JEDECSolidStateTechnologyAssociation 3103North1OthStreet.Suite240South Arlington,Virginia22201-2107 orcall(703)907-7559 JEDECStandardno,79-4A DDR4SDRAMSTANDARD (FromJEDECBoardBallotJCB-12-40,formulatedunderthecognizanceoftheJC-423Subcommitteeon DRAMMemories Contents 1.Scope 2.DDR4SDRAMPackagePinoutandAddressing 2.1DDR4SDRAMRowforx4X8andx16 2.2DDR4SDRAMBallPitch 2.3DDR4SDRAMColumnsforX4x8andx16 24DDR4SDRAMX4/8BalloutusingMO207…… 2.5DDR4SDRAMX16BalloutusingMO-207 2.6PinoutDescription... 2.7DDR4SDRAMAddressing “=a 3.FunctionalDescription 3.1SimplifiedStateDiagram 3.2BasicFunctionality 22235788999 3.3RESETandInitializationprocedure 3.3.1Power-upInitializationSequence 3.3.2ResetInitializationwithstablepower 11 3.4RegisterDetinition 12 3.4.1Programmingthemoderegisters 12 3.5ModeRegister 13 4.DDR4SDRAMCommandDescriptionandOperation 24 4.1Commandtruthtable 24 4.2CKETruthTable 25 4.3BurstLength,Typeandorder 26 4.3.1bl8Burstorderwithcrcenabled 26 4.4DLL-offModeDLLon/offSwitchingprocedure 27 4.4.1DLLon/offswitchingprocedure 27 4.4.2DLL“on"todll“offprocedure 27 4.4.3DLL“offtodll“on"Procedure 28 4.5DLL-offMode 4.6InputClockFrequencyChange 30 4.7WriteLeveling 31 4.7.1DRAMsettingforwriteleveling&DRAMterminationfunctioninthatmode 32 4.7.2ProcedureDescription 4.7.3WriteLevelingModeExit 4.8TemperaturecontrolledRefreshmodes 34 4.8.1Normaltemperaturemode 4 4.8.2EXtendedtemperaturemode 4.9FineGranularityRefreshMode 35 4.9.1ModeRegisterandCommandTruthTable 35 4.9.2tREFIandtRFCparameters 35 4.9.3ChangingRefreshRate 4.9.4UsagewithTemperatureControlledRefreshmode 4.9.5SelfRefreshentryandexit 4.10MultiPurposeRegister 37 4.10.1DQTrainingwithMPR 37 4.10.2MR3definition 37 4.10.3MPRReads 38 4.10.4MPRWrites 40 4.10.5MPRReadDataformat “ 43 4.11DataMask(DM),DataBusInversion(DBI)andTDQs 48 4.12ZQCalibrationCommands 50 JEDECStandardno.79-4A 4.12.1ZQCalibrationDescription “ 50 4.13DQVrefTraining 51 4.14PerDRAMAddressability. 4.15CALMode(Cs_ntoCommandAddressLatency) 59 4.15.1CALModeDescription 4.16CRC 61 4.16.1CRCPolynomialandlogicequation 1自 61 4.16.2CRCdatabitmappingforx8devices .63 4.16.3CRCdatabitmappingforx4devices asa8saaaa8aiaaas8a8a8aadadat .63 4.16.4CRCdatabitmappingforx16devices 4.16.5WriteCRcforx4,x8andx16devices .64 4.16.6CRCErrorHandling 64 4.16.7CRCFrameformatwithbC4 65 4.16.8SimultaneousDMandCRCFunctionality 4.17CommandAddressParity(CAParity) 68 4.17.1CAParityErrorLogReadout 4.18Controlgeardownmode 74 4.19DDR4KeyCoreTiming 77 4.20ProgrammablePreamble .....B 80 4.20.1WritePreamble 80 420.2ReadPreamble 81 4.20.3ReadPreambleTraining 82 4.21Postamble 82 4.21.1ReadPostamble ·.:.:::::. 82 4.212WritePostamble 82 4.22ACTIVATECommand 82 4.23PrechargeCommand... 83 4.24Readoperation 83 4.24.1READTimingDefinitions 83 4.24.1.1READTiming;ClocktoDataStroberelationship 85 4.24.1.2READTimingDataStrobetodatarelationship 86 4.24.1.3tLZ(DQS),tLZ(DQ),thz(DQS),tHZ(DQ)Calculation 87 4.24.1.4tRPRECalculation 4.24.1.5tRPSTCalculation 89 4.24.2READBurstOperation 90 4.24.3BurstReadOperationfollowedbyaPrecharge 101 4.24.4BurstReadOperationwithReadDBI(DataBusInversion 103 4.24.5BurstReadOperationwithCommand/AddressParity 104 4.24.6Readtowritewithwritecrc .105 4.24.7ReadtoReadwithCstoCALatency 106 4.25WriteOperation 107 4.25.1WriteBurstoperation 107 4.26Refreshcommand 123 4.27SelfrefreshOperation .124 4.27.1LowPowerautoselfRefresh ……126 4.28Powerdownmode 127 4.28.1Power-DownEntryandexit 127 4.28.2Power-Downclarifications 132 4.29MaximumPowerSavingMode 132 4.29.1Maximumpowersavingmode 132 4.29.2Modeentry……………… .132 4.29.3CKEtransitionduringthemode 133 4.29.4Modeexit 134 4.29.5TimingparameterbinofMaximumPowerSavingModeforDDR4-1600/1866/2133/2400/2666/3200134 4.30ConnectivityTestMode 135 430.1Introduction 135 4.30.2PinMapping… 135 4.30.3LogicEquations 136 4.30.3.1MinTermEquations.............. 136 JEDECStandardno,79-4A 4.30.3.2Outputequationsforx16devices 136 4.30.3.3Outputequationsforx8devices...................... 136 4.30.3.4OutputequationsforX4devices 4.30.4TimingRequirement.…… 137 4.31CLKtoReaddQStimingparameters “. 137 5.On-DieTermination 139 5.1ODTModeRegisterandodTStateTable 139 5.2SynchronousOdTMode 141 5.2.1ODTLatencyandPostedODT 142 5.2.2Timingparameters 142 5.2.3OdTduringReads:…… 143 5.3DynamicODT 144 5.3.1FunctionalDescription .144 5.3.2ODTTimingDiagrams 145 5.4AsynchronousODTmode .146 5.5OdTbufferdisabledmodeforpowerdown 147 5.6ODTTimingDefinitions 148 5.6.1TestLoadforODTTimings .148 5.6.2ODTTimingDefinitions 148 6.AbsoluteMaximumRatings 150 7.AC&dcOperatingconditions 151 7.1ACanddcInputMeasurementLevels:VREFTolerances 151 7.2ACandDCLogicInputLevelsforDifferentialSignals 152 7.2.1Differentialsignaldefinition :: 152 7.2.2Differentialswingrequirementsforclock(CKt-CKc 152 7.2.3Single-endedrequirementsfordifferentialsignals 153 7.2.4AddressandControlOvershootandUndershootspecifications 153 7.2.5ClockOvershootandUndershootSpecifications 154 7.2.6Data,StrobeandmaskOvershootandUndershootspecifications 15 7.3SlewRateDefinitionsforDifferentialInputSignals(CK) 156 7.4DifferentialInputCrossPointVoltage 157 7.5CMOSrailtorailInputLevels…… 159 7.5.1CMOSrailtorailInputLevelsforRESEtn .159 7.6AC&dclogicinputlevelsforsingle-endedsignals ..159 8.ACanddCoutputMeasurementlevels 160 8.1OutputDriverDCElectricalCharacteristic 160 8.1.1AlertnoutputDriveCharacteristic .161 8.2Single-endedAC&dCoutputLevels 162 8.3DifferentialACDCOutputLevels 162 8.4Single-endedOutputSlewRate ..162 8.5DifferentialOutputSlewRate “ 163 9.SpeedBin...........................................164 9.1SpeedBinTableNote 168 10.DDandidDQSpecificationParametersandTestconditions.............. 169 10.1IDD.IPPandIDDQMeasurementConditions .169 10.2IDDSpecifications 184 11.Input/OutputCapacitance 186 12.ElectricalCharacteristicsActiming 188 12.1ReferenceLoadforactimingandoutputslewRate 188 12.2tREFI 188 12.3TimingParametersbySpeedGrade 189 12.4TheDQinputreceivercompliancemaskforvoltageandtimingisshowninthefigurebelow........199 12.5DDR4Functionmatrix 204 AnnexaDifferencesbetweenJESD79-4AandJESD79-4 .207 JEDECStandardno.79-4A JEDECStandardno,79-4A Page1 Scope ThisdocumentdefinestheDDR4SDRAMspecification,includingfeatures,functionalities,ACandDCcharacteristics,packages,and ball/signalassignments.ThepurposeofthisstandardistodefinetheminimumsetofrequirementsforJEDECcompliant2Gb through16Gbforx4,x8,andx16DDR4SDRAMdevices.ThisstandardwascreatedbasedontheDDR3standard(JESD79-3)and someaspectsoftheDDRandDDR2standards(JESD79,JESD79-2 EachaspectofthechangesforDDR4SDRAMoperationwereconsideredandapprovedbycommitteeballot(s).Theaccumulationof theseballotswerethenincorporatedtopreparethisJESD79-4specifications,replacingwholesectionsandincorporatingthe changesintoFunctionaldescriptionandoperation JEDECStandardNo.79-4A Page2 DDR4SDRAMPackagePinoutandaddressing 2.1DDR4SDRAMRowforX4X8andX16 TheDDR4SDRAMX4/x8componentwillhave13electricalrowsofballs.Electricalisdefinedasrowsthatcontainsignalballor power/groundballs.Theremaybeadditionalrowsofinactiveballsformechanicalsupport TheDDR4SDRAMX16componentwillhave16electricalrowsofballs.Theremaybeadditionalrowsofinactiveballsformechanical support 2.2DDR4SDRAMBallPitch TheDDR4SDRAMcomponentwilluseaballpitchof0.8mmby0.8mm Thenumberofdepopulatedcolumnsis3 2.3DDR4SDRAMColumnsforX4X8andx16 TheDDR4SDRAMX4/x8andx16componentwillhave6electricalcolumnsofballsin2setsof3columns. TherewillbecolumnsbetweentheelectricalcolumnswheretherearenoballspopulatedThenumberofthesecolumnsis3 Electricalisdefinedascolumnsthatcontainsignalballorpower/groundballs.Theremaybeadditionalcolumnsofinactiveballsfor mechanicalsupport 2.4DDR4SDRAMX4/8BalloutusingMo-207 1 2 3 456 DMn,DBln VDD DQsc TDaSt2 VSSQ (NC) VPP VDDQ DQSc DQ1 VDDQ ZQ VDDQ DQ0 DOst VDD VSS DDC DQ4 DQ5 DQ2 DQ3 VSSQ BCDEFGHJKLM (NC) (NC) DQ6 DQ7 VSS VDDQ VSS (NC) VDDQ (NC) VDD c2)5 ODT CKt CKC VDD ODT1 VSS (c0)5 TEN CKE16 CKE csn c1)5 cs1n°Nc VDD WEn A14 ACtn CASn RASn A15 A16 VSS ABCDEFGHJK VREFCA BGO A10 A12 AP BCn BG1 VDD VSS BAO A4 A3 BA1 VSS RESETn A6 AO A1 A5 ALERTn VDD A8 A2 A9 A7 VPP M A17 VSS A11 PAR (NC)4 A13 VDD N NoTE1ThesepinsarenotconnectedfortheX4configuration NoTE2TDQstisnotvalidforthex4configuration notE3TDQscisnotvalidforthex4configuration NoTE4A17isonlydefinedforthex4configuration NoTE5Thesepinsareforstackedcomponentsuchas3DSFormonopackage,thesepinsareNC NOTE6ODT1/CKE1/CS1nareusedtogetheronlyforDDP. NOTE7TENisoptionalfor8Gbandabove.ThispinisnotconnectedifTENisnotsupported Figure1-DDR4BallAssignmentsforthex4/8component