乒乓ram代码及仿真波形.pdf

moduletop (inputclk,inputrst_n,input[15:0]in1,inputstart,inputends,outputreg[15:0]out); wire[3:0]waddra; wire[3:0]raddra; wire[15:0]dataa; wire[3:0]waddrb; wire[3:0]raddrb; wireppang; wire[15:0]data_out0; wire[15:0]data_out1; wirewr0; wirewr1;