1. 首页
  2. 行业
  3. 嵌入式
  4. RESEARCH AND DESIGN OF LOW JITTER WIDE LOCKINGRANGE

RESEARCH AND DESIGN OF LOW JITTER WIDE LOCKINGRANGE

上传者: 2019-07-27 10:41:32上传 PDF文件 771.77KB 热度 23次
PHASE-LOCKEDloops(PLLs)anddelay-lockedloops(DLLs)areoftenusedinintegratedcircuitsinordertocompensateforclockdistributiondelaysandtoimproveoverallsystemtiming.PLLsarealsowidelyusedinclockrecoveryandfrequencysynthesis.WhencomparedtotraditionalimplementationsofPLLsandDLLs,anall-digitalap
用户评论